Lines Matching full:msp430
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
14 #include "MSP430.h"
37 #define DEBUG_TYPE "msp430-lower"
40 "msp430-no-legal-immediate", cl::Hidden,
49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
56 setStackPointerRegisterToSaveRestore(MSP430::SP);
368 // tests/codegen/msp430/shift-amount-threshold-b.ll
376 // MSP430 Inline Assembly Support
403 return std::make_pair(0U, &MSP430::GR8RegClass);
405 return std::make_pair(0U, &MSP430::GR16RegClass);
460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
464 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
599 // MSP430 target does not yet support tail call optimization.
654 Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
784 unsigned R12 = MSP430::R12;
856 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
1197 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1297 MSP430::R4, VT);
1403 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1408 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1429 case MSP430::Shl8:
1430 Opc = MSP430::ADD8rr;
1431 RC = &MSP430::GR8RegClass;
1433 case MSP430::Shl16:
1434 Opc = MSP430::ADD16rr;
1435 RC = &MSP430::GR16RegClass;
1437 case MSP430::Sra8:
1438 Opc = MSP430::RRA8r;
1439 RC = &MSP430::GR8RegClass;
1441 case MSP430::Sra16:
1442 Opc = MSP430::RRA16r;
1443 RC = &MSP430::GR16RegClass;
1445 case MSP430::Srl8:
1447 Opc = MSP430::RRC8r;
1448 RC = &MSP430::GR8RegClass;
1450 case MSP430::Srl16:
1452 Opc = MSP430::RRC16r;
1453 RC = &MSP430::GR16RegClass;
1455 case MSP430::Rrcl8:
1456 case MSP430::Rrcl16: {
1457 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1458 .addReg(MSP430::SR).addImm(1);
1461 unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1462 ? MSP430::RRC16r : MSP430::RRC8r;
1492 Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1493 Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1503 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1505 BuildMI(BB, dl, TII.get(MSP430::JCC))
1514 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1517 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1521 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1522 .addReg(MSP430::SR).addImm(1);
1523 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1530 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1532 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1538 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1551 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1552 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1553 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1554 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1560 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1591 BuildMI(BB, dl, TII.get(MSP430::JCC))
1607 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())