Lines Matching +full:bd +full:- +full:address

1 //===-- M68kInstrFormats.td - M68k Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===//
16 ///  02   M68000    An                       a       address register direct
17 ///  03   M68000    (An)                     j       address register indirect
18 ///  04   M68000    (An)+                    o       address register indirect with postincrement
19 ///  05   M68000    -(An)                    e       address register indirect with predecrement
20 ///  06   M68000    (d16,An)                 p       address register indirect with displacement
21 ///  10   M68000    (d8,An,Xn.L)             f       address register indirect with index and scale…
22 ///  07   M68000    (d8,An,Xn.W)             F       address register indirect with index and scale…
23 ///  12   M68020    (d8,An,Xn.L,SCALE)       g       address register indirect with index
24 ///  11   M68020    (d8,An,Xn.W,SCALE)       G       address register indirect with index
25 ///  14   M68020    ([bd,An],Xn.L,SCALE,od)  u       memory indirect postindexed mode
26 ///  13   M68020    ([bd,An],Xn.W,SCALE,od)  U       memory indirect postindexed mode
27 ///  16   M68020    ([bd,An,Xn.L,SCALE],od)  v       memory indirect preindexed mode
28 ///  15   M68020    ([bd,An,Xn.W,SCALE],od)  V       memory indirect preindexed mode
29 ///  20   M68000    abs.L                    b       absolute long address
30 ///  17   M68000    abs.W                    B       absolute short address
36 ///  27   M68020    ([bd,PC],Xn.L,SCALE,od)  x       program counter memory indirect postindexed mo…
37 ///  26   M68020    ([bd,PC],Xn.W,SCALE,od)  X       program counter memory indirect postindexed mo…
38 ///  31   M68020    ([bd,PC,Xn.L,SCALE],od)  y       program counter memory indirect preindexed mode
39 ///  30   M68020    ([bd,PC,Xn.W,SCALE],od)  Y       program counter memory indirect preindexed mode
61 //===----------------------------------------------------------------------===//
66 /// d -> r, a -> r
68 //===----------------------------------------------------------------------===//
70 //===----------------------------------------------------------------------===//
126   // 16-bit Displacement
135   // 16-bit Displacement
171 // abs.W -> size_w_l = false
172 // abs.L -> size_w_l = true
181   // Absolute address
210 // using the effective address field in the operation word. The effective address
211 // is composed of two 3-bit fields: the mode field and the register field. The
212 // value in the mode field selects the different address modes. The register
213 // field contains the number of a register.  The effective address field may
215 // information, called the effective address extension, is contained in the
217 // effective address modes are grouped into three categories: register direct,