Lines Matching +full:32 +full:- +full:bits
1 // LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd/sd - destination register operand.
14 // rj/rk/sj - source register operand.
15 // immN/ptr - immediate data operand.
23 //===----------------------------------------------------------------------===//
25 // 1R-type (no outs)
27 class NoDstFmt1R<bits<32> op>
30 bits<5> rj;
32 let Inst{31-0} = op;
33 let Inst{9-5} = rj;
36 // 1RI3-type (no outs)
38 class NoDstFmt1RI3<bits<32> op>
41 bits<3> imm3;
42 bits<5> rj;
44 let Inst{31-0} = op;
45 let Inst{12-10} = imm3;
46 let Inst{9-5} = rj;
49 // 1RI4-type (no outs)
51 class NoDstFmt1RI4<bits<32> op>
54 bits<4> imm4;
55 bits<5> rj;
57 let Inst{31-0} = op;
58 let Inst{13-10} = imm4;
59 let Inst{9-5} = rj;
62 // 1RI4-type
64 class Fmt1RI4<bits<32> op>
67 bits<4> imm4;
68 bits<5> rd;
70 let Inst{31-0} = op;
71 let Inst{13-10} = imm4;
72 let Inst{4-0} = rd;
75 // 1RI5-type (no outs)
77 class NoDstFmt1RI5<bits<32> op>
80 bits<5> imm5;
81 bits<5> rj;
83 let Inst{31-0} = op;
84 let Inst{14-10} = imm5;
85 let Inst{9-5} = rj;
88 // 1RI5I4-type (no outs)
90 class NoDstFmt1RI5I4<bits<32> op>
93 bits<5> imm5;
94 bits<5> rj;
95 bits<4> imm4;
97 let Inst{31-0} = op;
98 let Inst{14-10} = imm5;
99 let Inst{9-5} = rj;
100 let Inst{3-0} = imm4;
103 // 1RI5I8-type
105 class Fmt1RI5I8<bits<32> op>
108 bits<8> imm8;
109 bits<5> imm5;
110 bits<5> rd;
112 let Inst{31-0} = op;
113 let Inst{17-10} = imm8;
114 let Inst{9-5} = imm5;
115 let Inst{4-0} = rd;
118 // 1RI6-type (no outs)
120 class NoDstFmt1RI6<bits<32> op>
123 bits<6> imm6;
124 bits<5> rj;
126 let Inst{31-0} = op;
127 let Inst{15-10} = imm6;
128 let Inst{9-5} = rj;
131 // 1RI8-type
133 class Fmt1RI8<bits<32> op>
136 bits<8> imm8;
137 bits<5> rd;
139 let Inst{31-0} = op;
140 let Inst{17-10} = imm8;
141 let Inst{4-0} = rd;
144 // 2R-type (no outs)
146 class NoDstFmt2R<bits<32> op>
149 bits<5> rk;
150 bits<5> rj;
152 let Inst{31-0} = op;
153 let Inst{14-10} = rk;
154 let Inst{9-5} = rj;
157 // 2RI4-type (no outs)
159 class NoDstFmt2RI4<bits<32> op>
162 bits<4> imm4;
163 bits<5> rk;
164 bits<5> rj;
166 let Inst{31-0} = op;
167 let Inst{14-10} = rk;
168 let Inst{9-5} = rj;
169 let Inst{3-0} = imm4;
172 // 2RI3-type
174 class Fmt2RI3<bits<32> op>
177 bits<3> imm3;
178 bits<5> rj;
179 bits<5> rd;
181 let Inst{31-0} = op;
182 let Inst{12-10} = imm3;
183 let Inst{9-5} = rj;
184 let Inst{4-0} = rd;
187 // 2RI4-type
189 class Fmt2RI4<bits<32> op>
192 bits<4> imm4;
193 bits<5> rj;
194 bits<5> rd;
196 let Inst{31-0} = op;
197 let Inst{13-10} = imm4;
198 let Inst{9-5} = rj;
199 let Inst{4-0} = rd;
203 class FmtGR2SCR<bits<32> op>
206 bits<5> rj;
207 bits<2> sd;
209 let Inst{31-0} = op;
210 let Inst{9-5} = rj;
211 let Inst{1-0} = sd;
215 class FmtSCR2GR<bits<32> op>
218 bits<2> sj;
219 bits<5> rd;
221 let Inst{31-0} = op;
222 let Inst{6-5} = sj;
223 let Inst{4-0} = rd;
227 class FmtJISCR<bits<32> op>
230 bits<21> imm21;
231 bits<5> rj;
233 let Inst{31-0} = op;
234 let Inst{25-10} = imm21{15-0};
235 let Inst{4-0} = imm21{20-16};
239 class FmtMFTOP<bits<32> op>
242 bits<5> rd;
244 let Inst{31-0} = op;
245 let Inst{4-0} = rd;
249 class FmtMTTOP<bits<32> op>
252 bits<3> ptr;
254 let Inst{31-0} = op;
255 let Inst{7-5} = ptr;