Lines Matching full:loongarch
14 #include "LoongArch.h"
31 "LoongArch Pre-RA pseudo instruction expansion pass"
33 "LoongArch pseudo instruction expansion pass"
116 case LoongArch::PseudoLA_PCREL:
118 case LoongArch::PseudoLA_GOT:
120 case LoongArch::PseudoLA_TLS_LE:
122 case LoongArch::PseudoLA_TLS_IE:
124 case LoongArch::PseudoLA_TLS_LD:
126 case LoongArch::PseudoLA_TLS_GD:
128 case LoongArch::PseudoLA_TLS_DESC_PC:
144 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
147 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
170 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
183 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
206 Large ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
209 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
212 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1)
215 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01)
221 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
223 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), Parts012)
227 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), DestReg)
244 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
257 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
270 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
289 unsigned ADD = STI.is64Bit() ? LoongArch::ADD_D : LoongArch::ADD_W;
290 unsigned ADDI = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
291 unsigned LD = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
295 MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
298 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
301 BuildMI(MBB, MBBI, DL, TII->get(ADDI), LoongArch::R4)
305 BuildMI(MBB, MBBI, DL, TII->get(LD), LoongArch::R1)
306 .addReg(LoongArch::R4)
309 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PseudoDESC_CALL), LoongArch::R1)
310 .addReg(LoongArch::R1)
314 .addReg(LoongArch::R4)
315 .addReg(LoongArch::R2);
406 case LoongArch::PseudoCopyCFR:
408 case LoongArch::PseudoLA_PCREL_LARGE:
410 case LoongArch::PseudoLA_GOT_LARGE:
412 case LoongArch::PseudoLA_TLS_IE_LARGE:
414 case LoongArch::PseudoLA_TLS_LD_LARGE:
416 case LoongArch::PseudoLA_TLS_GD_LARGE:
418 case LoongArch::PseudoLA_TLS_DESC_PC_LARGE:
420 case LoongArch::PseudoCALL:
421 case LoongArch::PseudoCALL_MEDIUM:
422 case LoongArch::PseudoCALL_LARGE:
424 case LoongArch::PseudoTAIL:
425 case LoongArch::PseudoTAIL_MEDIUM:
426 case LoongArch::PseudoTAIL_LARGE:
459 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::SET_CFR_FALSE), DestReg);
461 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::BCEQZ))
465 BuildMI(FalseBB, DL, TII->get(LoongArch::SET_CFR_TRUE), DestReg);
538 Register ScratchReg = LoongArch::R20; // $t8
543 auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), DestReg);
544 auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), ScratchReg)
545 .addReg(LoongArch::R0);
546 auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), ScratchReg)
549 auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), ScratchReg)
579 return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
588 return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
597 return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
606 return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
615 return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
637 Register ScratchReg = LoongArch::R20; // $t8
642 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), LoongArch::R4)
644 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), ScratchReg)
645 .addReg(LoongArch::R0)
647 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), ScratchReg)
650 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), ScratchReg)
653 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADD_D), LoongArch::R4)
655 .addReg(LoongArch::R4);
656 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LD_D), LoongArch::R1)
657 .addReg(LoongArch::R4)
659 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PseudoDESC_CALL), LoongArch::R1)
660 .addReg(LoongArch::R1)
662 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADD_D), DestReg)
663 .addReg(LoongArch::R4)
664 .addReg(LoongArch::R2);
690 Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
702 IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
703 Register ScratchReg = IsTailCall ? LoongArch::R20 : LoongArch::R1;
705 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCADDU18I), ScratchReg);
721 IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
722 Register AddrReg = IsTailCall ? LoongArch::R19 : LoongArch::R1;
726 unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
746 INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "loongarch-prera-expand-pseudo",
749 INITIALIZE_PASS(LoongArchExpandPseudo, "loongarch-expand-pseudo",