Lines Matching +full:hi +full:- +full:fi
1 //===-- LanaiISelDAGToDAG.cpp - A dag to dag inst selector for Lanai ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "lanai-isel"
37 #define PASS_NAME "Lanai DAG->DAG Pattern Instruction Selection"
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
44 // LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
46 //===----------------------------------------------------------------------===//
64 // Instruction Selection not handled by the auto-generated tablgen
68 // not handled by the auto-generated tablgen
79 // getI32Imm - Return a target constant with the specified value, of type i32.
81 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
90 // Fits in 21-bit signed immediate and two low-order bits are zero.
114 int32_t Imm = CN->getSExtValue();
115 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
134 // Fits in 16-bit signed immediate.
135 if (isInt<16>(CN->getSExtValue())) {
136 int16_t Imm = CN->getSExtValue();
137 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
138 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
139 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
147 // Fits in 10-bit signed immediate.
148 if (isInt<10>(CN->getSExtValue())) {
149 int16_t Imm = CN->getSExtValue();
150 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
151 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
152 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
158 // if Address is FI, get the TargetFrameIndex.
160 Base = CurDAG->getTargetFrameIndex(
161 FIN->getIndex(),
162 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
163 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
164 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
176 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
177 // Addresses of the form FI+const
179 if ((RiMode && isInt<16>(CN->getSExtValue())) ||
180 (!RiMode && isInt<10>(CN->getSExtValue()))) {
181 // If the first operand is a FI, get the TargetFI Node
184 Base = CurDAG->getTargetFrameIndex(
185 FIN->getIndex(),
186 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
191 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32);
202 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
203 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
250 // if Address is FI, get the TargetFrameIndex.
263 // Skip addresses of the form FI OP const
265 if (isInt<16>(CN->getSExtValue()))
268 // Skip addresses with hi/lo operands
269 if (Addr.getOperand(0).getOpcode() == LanaiISD::HI ||
272 Addr.getOperand(1).getOpcode() == LanaiISD::HI ||
280 AluOp = CurDAG->getTargetConstant(AluCode, SDLoc(Addr), MVT::i32);
311 unsigned Opcode = Node->getOpcode();
314 if (Node->isMachineOpcode()) {
315 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
319 // Instruction Selection not handled by the auto-generated tablegen selection
321 EVT VT = Node->getValueType(0);
328 if (ConstNode->isZero()) {
329 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
335 if (ConstNode->isAllOnes()) {
336 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
355 SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32);
356 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
357 EVT VT = Node->getValueType(0);
358 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
360 if (Node->hasOneUse()) {
361 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
364 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
367 // createLanaiISelDag - This pass converts a legalized DAG into a
368 // Lanai-specific DAG, ready for instruction scheduling.