Lines Matching +full:coexist +full:- +full:support
1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/raw_ostream.h"
59 DisablePacketizer("disable-packetizer", cl::Hidden,
62 static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
67 "hexagon-packetize-volatiles", cl::Hidden, cl::init(true),
68 cl::desc("Allow non-solo packetization of volatile memory references"));
71 EnableGenAllInsnClass("enable-gen-insn", cl::Hidden,
75 DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::Hidden,
76 cl::desc("Disable vector double new-value-stores"));
125 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
131 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
189 for (++I; I != E && I->isBundledWithPred(); ++I)
199 MachineInstr &SingleI = *BundleIt->getNextNode();
202 BundleIt->eraseFromParent();
220 HII->genAllInsnTimingClasses(MF);
230 // Loop over all basic blocks and remove KILL pseudo-instructions
244 // TinyCore with Duplexes: Translate to big-instructions.
246 HII->translateInstrsForDup(MF, true);
252 // Find the first non-boundary starting from the end of the last
255 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
260 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
273 // TinyCore with Duplexes: Translate to tiny-instructions.
275 HII->translateInstrsForDup(MF, false);
295 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
296 bool Avail = ResourceTracker->canReserveResources(*ExtMI);
298 ResourceTracker->reserveResources(*ExtMI);
306 if (DepReg == HRI->getRARegister())
309 if (HII->isDeallocRet(MI))
310 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
313 // Call-like instructions can be packetized with preceding instructions
348 /// Returns true if the instruction modifies a callee-saved register.
351 const MachineFunction &MF = *MI.getParent()->getParent();
352 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
359 // new-value store.
362 // Vector stores can be predicated, and can be new-value stores, but
365 if (HII->isHVXVec(MI) && MI.mayStore())
367 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
369 // If the class is not PredRegs, it could only apply to new-value stores.
370 return HII->mayBeNewStore(MI);
380 int CurOpcode = HII->getDotCurOp(MI);
381 MI.setDesc(HII->get(CurOpcode));
388 LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
389 if (HII->isDotCurInst(*BI)) {
394 for (auto &MO : BI->operands())
395 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
401 // We did not find a use of the CUR, so de-cur it.
402 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
403 LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
410 if (!HII->isHVXVec(MI))
412 if (!HII->isHVXVec(*MII))
416 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
419 if (!HII->mayBeCurLoad(MI))
423 if (PacketSU->getInstr()->isInlineAsm())
445 LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
446 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
464 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
466 NewOpcode = HII->getDotNewOp(MI);
467 MI.setDesc(HII->get(NewOpcode));
472 int NewOpcode = HII->getDotOldOp(MI);
473 MI.setDesc(HII->get(NewOpcode));
490 int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
491 if (HII->isValidOffset(Opc, NewOff, HRI)) {
517 assert(SUI->getInstr() && SUJ->getInstr());
518 MachineInstr &MI = *SUI->getInstr();
519 MachineInstr &MJ = *SUJ->getInstr();
522 if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
525 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
533 for (const auto &PI : SUI->Preds)
538 if (!HII->getIncrementValue(MJ, Incr))
542 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
554 if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
569 if (!HII->isPredicated(MI))
571 if (HII->isPredicatedTrue(MI))
578 assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
612 return MI.getOperand(MI.getNumOperands()-1);
637 // 1. If an instruction uses auto-increment, its address register cannot
638 // be a new-value register. Arch Spec 5.4.2.1
639 // 2. If an instruction uses absolute-set addressing mode, its address
640 // register cannot be a new-value register. Arch Spec 5.4.2.1.
641 // 3. If an instruction produces a 64-bit result, its registers cannot be used
642 // as new-value registers. Arch Spec 5.4.2.2.
643 // 4. If the instruction that sets the new-value register is conditional, then
644 // the instruction that uses the new-value register must also be conditional,
654 if (!HII->mayBeNewStore(MI))
665 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
670 // New-value stores are of class NV (slot 0), dual stores require class ST
673 SUnit *PacketSU = MIToSUnit.find(I)->second;
674 if (PacketSU->getInstr()->mayStore())
680 if (HII->isPostIncrement(MI) &&
685 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
687 // If source is post_inc, or absolute-set addressing, it can not feed
690 // memw(r30 + #-1404) = r2.new -> can not be new value store
700 if (HII->isPredicated(PacketMI)) {
701 if (!HII->isPredicated(MI))
715 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
722 // Get predicate register used in new-value store instruction.
727 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
734 // New-value register producer and user (store) need to satisfy these
737 // 2) If producer of the new-value register is .new predicated then store
740 // 3) Both new-value register producer and user should have same predicate
741 // sense, i.e, either both should be negated or both should be non-negated.
743 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
748 // Make sure that other than the new-value register no other store instruction
759 SUnit *TempSU = MIToSUnit.find(I)->second;
760 MachineInstr &TempMI = *TempSU->getInstr();
773 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
777 // Make sure that for non-POST_INC stores:
783 if (!HII->isPostIncrement(MI)) {
784 for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
793 // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
801 if (R == DepReg || HRI->isSuperRegister(DepReg, R))
805 // Handle imp-use of super reg case. There is a target independent side
807 // just-in-case. For example, we cannot newify R2 in the following case:
823 if (!HII->mayBeNewStore(MI))
827 MachineInstr &PacketMI = *PacketSU->getInstr();
854 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
860 const MachineInstr &PI = *PacketSU->getInstr();
878 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
884 return HII->predCanBeUsedAsDotNew(PI, DepReg);
886 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
891 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) :
892 HII->getDotNewPredOp(MI, MBPI);
893 const MCInstrDesc &D = HII->get(NewOpcode);
895 bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
919 // Anti-dep between c) and b) is irrelevant for this case
922 SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
926 if (!HII->isPredicated(*I))
930 SUnit *PacketSU = MIToSUnit.find(I)->second;
935 if (PacketSU->isSucc(PacketSUDep)) {
936 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
937 auto &Dep = PacketSU->Succs[i];
953 assert(QII->isPredicated(MI) && "Must be predicated instruction");
996 SUnit *PacketSU = MIToSUnit.find(I)->second;
999 if (PacketSU->isSucc(SU)) {
1000 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
1001 auto Dep = PacketSU->Succs[i];
1009 // data dep to candidate on the register we care about - c) in the
1030 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1062 auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1063 return !IS->getUnits();
1085 if (HII->isSolo(MI))
1099 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1100 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1101 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1108 const MachineFunction *MF = MI.getParent()->getParent();
1109 if (MF->getSubtarget<HexagonSubtarget>().hasV60OpsOnly() &&
1126 // New-value stores cannot coexist with any other stores.
1141 // These instructions can only be grouped with ALU32 or non-floating-point
1156 // I and J cannot coexist.
1214 if (HII->isPredicated(I) || HII->isPredicated(J))
1236 // A save callee-save register function call can only be in a packet
1237 // with instructions that don't write to the callee-save registers.
1238 if ((HII->isSaveCalleeSavedRegsCall(I) &&
1240 (HII->isSaveCalleeSavedRegsCall(J) &&
1248 // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1250 // a new-value compare jump or a dealloc_return.
1251 auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1252 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1254 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1259 if (HII->isLoopN(I) && isBadForLoopN(J))
1261 if (HII->isLoopN(J) && isBadForLoopN(I))
1266 return HII->isDeallocRet(I) &&
1286 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1308 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1313 bool MopStI = HII->isMemOp(I) || StoreI;
1314 bool MopStJ = HII->isMemOp(J) || StoreJ;
1319 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1326 assert(SUI->getInstr() && SUJ->getInstr());
1327 MachineInstr &I = *SUI->getInstr();
1328 MachineInstr &J = *SUJ->getInstr();
1354 // Dual-store does not allow second store, if the first store is not
1364 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1375 // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1376 if (PI->isCall()) {
1388 if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1389 HII->isLoopN(*PI)) {
1395 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1407 if (!SUJ->isSucc(SUI))
1410 for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1414 if (SUJ->Succs[i].getSUnit() != SUI)
1417 SDep::Kind DepType = SUJ->Succs[i].getKind();
1436 DepReg = SUJ->Succs[i].getReg();
1437 RC = HRI->getMinimalPhysRegClass(DepReg);
1440 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1443 if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1454 if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1455 if (HII->isHVXVec(I))
1459 // For instructions that can be promoted to dot-new, try to promote.
1469 if (HII->isNewValueJump(I))
1475 if (HII->isPredicated(I) && HII->isPredicated(J) &&
1485 // There will be an output dependence between (1)->(2) and (2)->(3).
1486 // However, there is no dependence edge between (1)->(3). This results
1499 // and non-control-flow instructions.
1532 bool NVStoreJ = HII->isNewValueStore(J);
1533 bool NVStoreI = HII->isNewValueStore(I);
1534 bool IsVecJ = HII->isHVXVec(J);
1535 bool IsVecI = HII->isHVXVec(I);
1539 if (LoadJ && LoadI && HII->isPureSlot0(J)) {
1551 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1584 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1599 // There are certain anti-dependencies that cannot be ignored.
1601 // J2_call ... implicit-def %r0 ; SUJ
1623 // Skip over remaining anti-dependences. Two instructions that are
1624 // anti-dependent can share a packet, since in most such cases all
1644 assert(SUI->getInstr() && SUJ->getInstr());
1645 MachineInstr &I = *SUI->getInstr();
1646 MachineInstr &J = *SUJ->getInstr();
1648 bool Coexist = !cannotCoexist(I, J);
1650 if (Coexist && !Dependence)
1653 // Check if the instruction was promoted to a dot-new. If so, demote it
1654 // back into a dot-old.
1671 // Putting I and J together would prevent the new-value jump from being
1677 if (!Coexist)
1695 unsigned Opc = MJ->getOpcode();
1698 if (HII->isMemOp(*MJ))
1700 if (MJ->mayLoad())
1702 if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1727 assert(ResourceTracker->canReserveResources(MI));
1729 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1738 ResourceTracker->reserveResources(MI);
1742 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1744 if (ResourceTracker->canReserveResources(NvjMI))
1745 ResourceTracker->reserveResources(NvjMI);
1754 assert(ResourceTracker->canReserveResources(MI));
1755 ResourceTracker->reserveResources(MI);
1760 assert(ResourceTracker->canReserveResources(NvjMI));
1761 ResourceTracker->reserveResources(NvjMI);
1772 ResourceTracker->reserveResources(MI);
1781 ResourceTracker->reserveResources(MI);
1797 unsigned R = ResourceTracker->getUsedResources(Idx++);
1812 MachineBasicBlock::instr_iterator NextMI = std::next(MI->getIterator());
1813 for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1824 HII->setBundleNoShuf(BundleMII);
1831 ResourceTracker->clearResources();
1844 auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
1854 // Check for SLOT0 only non-duplexable instruction in packet.
1856 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);
1858 int Opcode = HII->getDuplexOpcode(MI, false);
1862 if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) {
1870 MIRef.setDesc(HII->get(Opcode));
1871 return ResourceTracker->canReserveResources(MIRef);
1888 auto *OldBB = OldPacketMIs.front()->getParent();
1890 if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1907 // non-zero even though we can have both .cur and .new in the same packet.
1921 for (auto &Pred : SUI->Preds)
1924 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1932 for (auto &Pred : SUI->Preds)
1950 //===----------------------------------------------------------------------===//
1952 //===----------------------------------------------------------------------===//