Lines Matching defs:MJ
429 MachineInstr &MJ = *MII;
432 MJ.dump();
436 for (auto &MO : MJ.operands())
514 /// Return true if we can update the offset in MI so that MI and MJ
519 MachineInstr &MJ = *SUJ->getInstr();
525 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
528 if (Reg != MJ.getOperand(BPJ).getReg())
538 if (!HII->getIncrementValue(MJ, Incr))
1099 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1100 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1101 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1103 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1105 // since every test would need to be repeated with the MI and MJ reversed.
1106 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1110 HII.isHVXMemWithAIndirect(MI, MJ))
1115 if (MI.mayStore() && HII.isRestrictNoSlot1Store(MJ) && HII.isPureSlot0(MJ))
1123 return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1124 MJ.isCall() || MJ.isTerminator();
1127 if (HII.isNewValueStore(MI) && MJ.mayStore())
1144 unsigned TJ = HII.getType(MJ);
1162 const MachineInstr &MJ) {
1163 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1694 for (auto *MJ : CurrentPacketMIs) {
1695 unsigned Opc = MJ->getOpcode();
1698 if (HII->isMemOp(*MJ))
1700 if (MJ->mayLoad())
1702 if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1855 for (auto &MJ : CurrentPacketMIs)
1856 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);
1861 for (auto &MJ : CurrentPacketMIs) {
1862 if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) {