Lines Matching defs:HII
116 const HexagonInstrInfo *HII = nullptr;
139 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
212 HII = HST.getInstrInfo();
220 HII->genAllInsnTimingClasses(MF);
246 HII->translateInstrsForDup(MF, true);
255 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
260 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
275 HII->translateInstrsForDup(MF, false);
295 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
309 if (HII->isDeallocRet(MI))
365 if (HII->isHVXVec(MI) && MI.mayStore())
367 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
370 return HII->mayBeNewStore(MI);
380 int CurOpcode = HII->getDotCurOp(MI);
381 MI.setDesc(HII->get(CurOpcode));
389 if (HII->isDotCurInst(*BI)) {
402 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
410 if (!HII->isHVXVec(MI))
412 if (!HII->isHVXVec(*MII))
416 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
419 if (!HII->mayBeCurLoad(MI))
464 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
466 NewOpcode = HII->getDotNewOp(MI);
467 MI.setDesc(HII->get(NewOpcode));
472 int NewOpcode = HII->getDotOldOp(MI);
473 MI.setDesc(HII->get(NewOpcode));
491 if (HII->isValidOffset(Opc, NewOff, HRI)) {
522 if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
525 if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
538 if (!HII->getIncrementValue(MJ, Incr))
542 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
554 if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
568 const HexagonInstrInfo *HII) {
569 if (!HII->isPredicated(MI))
571 if (HII->isPredicatedTrue(MI))
577 const HexagonInstrInfo *HII) {
578 assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
654 if (!HII->mayBeNewStore(MI))
665 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
680 if (HII->isPostIncrement(MI) &&
681 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
685 if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
686 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
700 if (HII->isPredicated(PacketMI)) {
701 if (!HII->isPredicated(MI))
743 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
744 getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
783 if (!HII->isPostIncrement(MI)) {
823 if (!HII->mayBeNewStore(MI))
854 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
878 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
884 return HII->predCanBeUsedAsDotNew(PI, DepReg);
886 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
891 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) :
892 HII->getDotNewPredOp(MI, MBPI);
893 const MCInstrDesc &D = HII->get(NewOpcode);
926 if (!HII->isPredicated(*I))
971 if (getPredicateSense(MI1, HII) == PK_Unknown ||
972 getPredicateSense(MI2, HII) == PK_Unknown)
1024 unsigned PReg1 = getPredicatedRegister(MI1, HII);
1025 unsigned PReg2 = getPredicatedRegister(MI2, HII);
1029 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1030 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1085 if (HII->isSolo(MI))
1107 const HexagonInstrInfo &HII) {
1110 HII.isHVXMemWithAIndirect(MI, MJ))
1115 if (MI.mayStore() && HII.isRestrictNoSlot1Store(MJ) && HII.isPureSlot0(MJ))
1127 if (HII.isNewValueStore(MI) && MJ.mayStore())
1144 unsigned TJ = HII.getType(MJ);
1163 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1214 if (HII->isPredicated(I) || HII->isPredicated(J))
1238 if ((HII->isSaveCalleeSavedRegsCall(I) &&
1240 (HII->isSaveCalleeSavedRegsCall(J) &&
1252 if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1254 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1259 if (HII->isLoopN(I) && isBadForLoopN(J))
1261 if (HII->isLoopN(J) && isBadForLoopN(I))
1266 return HII->isDeallocRet(I) &&
1286 assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1308 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1313 bool MopStI = HII->isMemOp(I) || StoreI;
1314 bool MopStJ = HII->isMemOp(J) || StoreJ;
1319 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1364 if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1389 HII->isLoopN(*PI)) {
1440 if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1454 if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1455 if (HII->isHVXVec(I))
1469 if (HII->isNewValueJump(I))
1475 if (HII->isPredicated(I) && HII->isPredicated(J) &&
1532 bool NVStoreJ = HII->isNewValueStore(J);
1533 bool NVStoreI = HII->isNewValueStore(I);
1534 bool IsVecJ = HII->isHVXVec(J);
1535 bool IsVecI = HII->isHVXVec(I);
1539 if (LoadJ && LoadI && HII->isPureSlot0(J)) {
1551 (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1698 if (HII->isMemOp(*MJ))
1702 if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1729 bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1742 bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1813 for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1824 HII->setBundleNoShuf(BundleMII);
1856 PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);
1858 int Opcode = HII->getDuplexOpcode(MI, false);
1862 if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) {
1870 MIRef.setDesc(HII->get(Opcode));
1924 HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))