Lines Matching defs:HexagonSubtarget

1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
13 #include "HexagonSubtarget.h"
76 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
90 HexagonSubtarget &
91 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
172 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
183 bool HexagonSubtarget::isHVXVectorType(EVT VecTy, bool IncludeBool) const {
211 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
246 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
259 void HexagonSubtarget::HVXMemLatencyMutation::apply(ScheduleDAGInstrs *DAG) {
298 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
310 void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
319   auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
378 void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
428 bool HexagonSubtarget::useAA() const {
436 void HexagonSubtarget::adjustSchedDependency(
513 void HexagonSubtarget::getPostRAMutations(
520 void HexagonSubtarget::getSMSMutations(
527 void HexagonSubtarget::anchor() {}
529 bool HexagonSubtarget::enableMachineScheduler() const {
535 bool HexagonSubtarget::usePredicatedCalls() const {
539 int HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
554 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
603 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
632 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
717 unsigned HexagonSubtarget::getL1CacheLineSize() const {
721 unsigned HexagonSubtarget::getL1PrefetchDistance() const {
725 bool HexagonSubtarget::enableSubRegLiveness() const { return true; }
727 Intrinsic::ID HexagonSubtarget::getIntrinsicId(unsigned Opc) const {