Lines Matching defs:const
108 const int Hexagon_MEMW_OFFSET_MAX = 4095;
109 const int Hexagon_MEMW_OFFSET_MIN = -4096;
110 const int Hexagon_MEMD_OFFSET_MAX = 8191;
111 const int Hexagon_MEMD_OFFSET_MIN = -8192;
112 const int Hexagon_MEMH_OFFSET_MAX = 2047;
113 const int Hexagon_MEMH_OFFSET_MIN = -2048;
114 const int Hexagon_MEMB_OFFSET_MAX = 1023;
115 const int Hexagon_MEMB_OFFSET_MIN = -1024;
116 const int Hexagon_ADDI_OFFSET_MAX = 32767;
117 const int Hexagon_ADDI_OFFSET_MIN = -32768;
137 static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
156 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
168 // const-extended and hence, it is not cheap.
187 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {
201 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
238 static inline void parseOperands(const MachineInstr &MI,
243 for (const MachineOperand &MO : MI.operands()) {
290 Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
291 int &FrameIndex) const {
305 const MachineOperand OpFI = MI.getOperand(1);
308 const MachineOperand OpOff = MI.getOperand(2);
319 const MachineOperand OpFI = MI.getOperand(2);
322 const MachineOperand OpOff = MI.getOperand(3);
338 Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
339 int &FrameIndex) const {
353 const MachineOperand &OpFI = MI.getOperand(0);
356 const MachineOperand &OpOff = MI.getOperand(1);
371 const MachineOperand &OpFI = MI.getOperand(1);
374 const MachineOperand &OpOff = MI.getOperand(2);
389 const MachineInstr &MI,
390 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
392 const MachineBasicBlock *MBB = MI.getParent();
407 const MachineInstr &MI,
408 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
410 const MachineBasicBlock *MBB = MI.getParent();
440 bool AllowModify) const {
607 int *BytesRemoved) const {
633 const DebugLoc &DL,
634 int *BytesAdded) const {
695 const MachineOperand &RO = Cond[1];
719 const MachineOperand &RO = Cond[1];
732 const HexagonInstrInfo *TII;
751 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
806 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
822 BranchProbability Probability) const {
829 const {
834 unsigned NumInstrs, BranchProbability Probability) const {
838 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
839 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
840 const MachineBasicBlock &B = *MI.getParent();
849 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
850 const MachineBasicBlock &B = *MI.getParent();
859 const DebugLoc &DL, MCRegister DestReg,
860 MCRegister SrcReg, bool KillSrc) const {
861 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
961 const TargetRegisterClass *RC,
962 const TargetRegisterInfo *TRI,
963 Register VReg) const {
1009 const TargetRegisterClass *RC,
1010 const TargetRegisterInfo *TRI,
1011 Register VReg) const {
1052 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1056 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1075 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1078 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1088 const GlobalValue *NameVar = Op0.getGlobal();
1089 const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar);
1116 const char *cstr = MF.createExternalSymbolName(NameStr);
1173 const MachineOperand &BaseOp = MI.getOperand(1);
1188 const MachineOperand &BaseOp = MI.getOperand(1);
1209 const MachineOperand &SrcOp = MI.getOperand(2);
1211 const MachineOperand &BaseOp = MI.getOperand(0);
1227 const MachineOperand &BaseOp = MI.getOperand(0);
1341 const MachineOperand &Op0 = MI.getOperand(0);
1342 const MachineOperand &Op1 = MI.getOperand(1);
1343 const MachineOperand &Op2 = MI.getOperand(2);
1344 const MachineOperand &Op3 = MI.getOperand(3);
1365 const MachineOperand &Op0 = MI.getOperand(0);
1366 const MachineOperand &Op1 = MI.getOperand(1);
1367 const MachineOperand &Op2 = MI.getOperand(2);
1368 const MachineOperand &Op3 = MI.getOperand(3);
1441 CrashPseudoSourceValue(const TargetMachine &TM)
1444 bool isConstant(const MachineFrameInfo *) const override {
1447 bool isAliased(const MachineFrameInfo *) const override {
1450 bool mayAlias(const MachineFrameInfo *) const override {
1453 void printCustom(raw_ostream &OS) const override {
1458 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1546 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1548 const DebugLoc &DL = MI.getDebugLoc();
1635 SmallVectorImpl<MachineOperand> &Cond) const {
1650 MachineBasicBlock::iterator MI) const {
1655 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1667 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1668 const uint64_t F = MI.getDesc().TSFlags;
1673 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1725 ArrayRef<MachineOperand> Pred2) const {
1732 bool SkipDead) const {
1733 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1735 for (const MachineOperand &MO : MI.operands()) {
1739 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1757 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1793 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1794 const MachineBasicBlock *MBB,
1795 const MachineFunction &MF) const {
1841 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1842 const MCAsmInfo &MAI,
1843 const TargetSubtargetInfo *STI) const {
1848 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1870 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1880 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1882 int64_t &Value) const {
1959 const MachineOperand &Op2 = MI.getOperand(2);
1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1971 const MachineInstr &MI,
1972 unsigned *PredCost) const {
1977 const TargetSubtargetInfo &STI) const {
1978 const InstrItineraryData *II = STI.getInstrItineraryData();
1979 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1987 const MachineInstr &MIa, const MachineInstr &MIb) const {
2001 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
2009 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
2021 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
2022 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
2044 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
2045 int &Value) const {
2050 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
2056 const MachineOperand &AddOp = MI.getOperand(2);
2067 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2072 ArrayRef<std::pair<unsigned, const char*>>
2073 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2076 static const std::pair<unsigned, const char*> Flags[] = {
2091 ArrayRef<std::pair<unsigned, const char*>>
2092 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2095 static const std::pair<unsigned, const char*> Flags[] = {
2101 Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2103 const TargetRegisterClass *TRC;
2118 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2122 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2123 const uint64_t F = MI.getDesc().TSFlags;
2127 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2131 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2140 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2146 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2147 const uint64_t F = MI.getDesc().TSFlags;
2161 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2195 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2210 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2211 const MachineInstr &ConsMI) const {
2214 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2241 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2252 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2260 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2261 const MachineInstr &MIb) const {
2267 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2272 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2286 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2287 const MCInstrDesc &MID = MI.getDesc();
2288 const uint64_t F = MID.TSFlags;
2308 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2310 const uint64_t F = MI.getDesc().TSFlags;
2315 for (const MachineOperand &MO : MI.operands())
2321 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2323 const uint64_t F = get(Opcode).TSFlags;
2328 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2329 const MachineInstr &J) const {
2337 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2348 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2362 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2380 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2381 unsigned offset) const {
2422 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2428 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2440 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2472 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2473 const uint64_t F = MI.getDesc().TSFlags;
2477 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2478 const uint64_t F = get(Opcode).TSFlags;
2482 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2486 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2490 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2494 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2495 const uint64_t F = MI.getDesc().TSFlags;
2499 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2500 const uint64_t F = get(Opcode).TSFlags;
2505 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2506 unsigned OperandNum) const {
2507 const uint64_t F = MI.getDesc().TSFlags;
2512 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2513 const uint64_t F = MI.getDesc().TSFlags;
2518 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2519 const uint64_t F = get(Opcode).TSFlags;
2524 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2525 const uint64_t F = MI.getDesc().TSFlags;
2530 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2531 const uint64_t F = get(Opcode).TSFlags;
2538 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2539 const uint64_t F = get(Opcode).TSFlags;
2543 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2544 const uint64_t F = get(Opcode).TSFlags;
2548 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2549 const uint64_t F = get(Opcode).TSFlags;
2555 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2562 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2640 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2641 const uint64_t F = MI.getDesc().TSFlags;
2645 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2655 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2666 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2671 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2676 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2681 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2687 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2688 const MachineInstr &MI2) const {
2705 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2706 const uint64_t V = getType(MI);
2711 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2749 const TargetRegisterInfo *TRI, bool Extend) const {
2958 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2962 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2963 const uint64_t F = get(MI.getOpcode()).TSFlags;
2964 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2970 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2971 const MachineInstr &ConsMI) const {
2984 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
3063 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
3064 const MachineInstr &MI2) const {
3073 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
3075 const TargetRegisterInfo *TRI) const {
3077 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3085 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
3086 const MachineInstr &Second) const {
3088 const MachineOperand &Op = Second.getOperand(0);
3097 const MachineOperand &Stored =
3102 const MachineOperand &Op = First.getOperand(i);
3110 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3115 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3124 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3159 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3164 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3165 const {
3176 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3177 const uint64_t F = MI.getDesc().TSFlags;
3183 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3187 const uint64_t F = MI.getDesc().TSFlags;
3191 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3192 const MachineInstr &ConsMI) const {
3209 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3210 MachineBasicBlock::const_instr_iterator BII) const {
3222 const MachineInstr &J = *MII;
3229 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3230 Register PredReg) const {
3231 for (const MachineOperand &MO : MI.operands()) {
3264 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3275 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3281 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3282 const uint64_t F = MI.getDesc().TSFlags;
3291 HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3292 LocationSize &AccessSize) const {
3310 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3316 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3323 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3324 unsigned &BasePos, unsigned &OffsetPos) const {
3361 MachineBasicBlock& MBB) const {
3418 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3419 const uint64_t F = MI.getDesc().TSFlags;
3426 const MachineInstr &MI) const {
3471 // Do not test for #u6 size since the const is getting extended
3513 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3514 const MachineInstr &GB) const {
3526 const MachineOperand &CmpOp = GA.getOperand(2);
3540 int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3541 bool ForBigCore) const {
3549 static const std::map<unsigned, unsigned> DupMap = {
3590 for (const auto &Iter : DupMap)
3597 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3609 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3629 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3730 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3771 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3772 const MachineBranchProbabilityInfo *MBPI) const {
3774 const MachineBasicBlock *Src = MI.getParent();
3775 const MachineOperand &BrTarget = MI.getOperand(1);
3777 const BranchProbability OneHalf(1, 2);
3779 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3780 const MachineBasicBlock *Dst) {
3787 const MachineBasicBlock *Dst = BrTarget.getMBB();
3800 const MachineBasicBlock &B = *MI.getParent();
3802 for (const MachineInstr &I : B) {
3822 for (const MachineBasicBlock *SB : B.successors()) {
3831 const MachineBasicBlock *BT = nullptr;
3832 for (const MachineOperand &Op : NextIt->operands()) {
3857 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3858 const MachineBranchProbabilityInfo *MBPI) const {
3872 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3924 const MachineInstr &MI) const {
3926 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4213 // Do not test for #u6 size since the const is getting extended
4303 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4308 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4328 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4329 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4330 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4333 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4346 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4372 SmallVectorImpl<MachineOperand> &Cond) const {
4380 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4391 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4392 const uint64_t F = MI.getDesc().TSFlags;
4405 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4423 const uint64_t F = MI.getDesc().TSFlags;
4433 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4445 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4446 const uint64_t F = MI.getDesc().TSFlags;
4452 bool ToBigInstrs) const {
4470 bool ToBigInstrs) const {
4480 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4488 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4491 const uint64_t F = MI.getDesc().TSFlags;
4501 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4511 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4512 const uint64_t F = MI.getDesc().TSFlags;
4525 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4550 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4569 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4573 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4581 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4596 const MachineBasicBlock &MBB = *MI.getParent();
4597 const MachineFunction *MF = MBB.getParent();
4598 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4608 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4615 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4616 const uint64_t F = MI.getDesc().TSFlags;
4620 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4621 const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4622 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4628 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4633 MachineBasicBlock::const_iterator BundleHead) const {
4642 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4656 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4676 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4698 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4705 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4716 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4717 const {
4722 setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
4731 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4733 const MachineOperand &Operand = MIB.getOperand(0);
4738 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4742 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4746 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4750 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4754 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4758 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
4762 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
4766 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
4770 MCInst HexagonInstrInfo::getNop() const {
4771 static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);