Lines Matching defs:HexagonInstrInfo

1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
13 #include "HexagonInstrInfo.h"
120 void HexagonInstrInfo::anchor() {}
122 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
156 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
187 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {
199 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
290 Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
338 Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
388 bool HexagonInstrInfo::hasLoadFromStackSlot(
406 bool HexagonInstrInfo::hasStoreToStackSlot(
436 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
606 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
629 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
732   const HexagonInstrInfo *TII;
806 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
820 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
826 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
833 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
857 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
958 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1006 void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1052 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1546 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1634 bool HexagonInstrInfo::reverseBranchCondition(
1649 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1655 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1667 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1672 bool HexagonInstrInfo::PredicateInstruction(
1724 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1730 bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,
1757 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1793 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1841 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1869 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1880 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1976 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1986 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
2044 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
2067 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2073 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2092 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2101 Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2118 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2122 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2127 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2131 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2140 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2146 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2195 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2210 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2241 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2252 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2260 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2267 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2272 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2286 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2308 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2321 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2328 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2337 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2348 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2362 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2380 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2422 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2428 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2440 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2472 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2477 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2482 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2486 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2490 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2494 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2499 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2505 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2512 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2518 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2524 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2530 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2538 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2543 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2548 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2555 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2562 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2640 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2645 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2655 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2666 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2671 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2676 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2681 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2687 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2705 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2711 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2748 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2958 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2962 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2970 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2984 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
3063 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
3072 bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
3085 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
3110 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3115 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3124 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3159 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3164 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3176 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3183 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3191 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3209 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3229 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3264 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3275 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3281 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3291 HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3323 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3360 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3418 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3425 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3513 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3540 int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3597 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3609 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3629 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3730 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3771 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3857 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3872 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3923 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
4303 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4307 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4327 std::optional<unsigned> HexagonInstrInfo::getOperandLatency(
4371 bool HexagonInstrInfo::getInvertedPredSense(
4380 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4391 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4405 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4433 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4445 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4451 void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
4469 void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,
4479 void HexagonInstrInfo::translateInstrsForDup(
4488 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4511 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4525 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4549 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4569 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4573 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4581 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4615 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4620 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4628 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4632 unsigned HexagonInstrInfo::nonDbgBundleSize(
4642 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4655 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4676 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4698 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4705 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4716 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4721 void HexagonInstrInfo::
4731 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4738 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4742 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4746 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4750 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4754 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4758 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
4762 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
4766 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
4770 MCInst HexagonInstrInfo::getNop() const {