Lines Matching defs:BaseOp

1173       const MachineOperand &BaseOp = MI.getOperand(1);
1174       assert(BaseOp.getSubReg() == 0);
1180           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1188       const MachineOperand &BaseOp = MI.getOperand(1);
1189       assert(BaseOp.getSubReg() == 0);
1197           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1202           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1211       const MachineOperand &BaseOp = MI.getOperand(0);
1212       assert(BaseOp.getSubReg() == 0);
1218           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1227       const MachineOperand &BaseOp = MI.getOperand(0);
1228       assert(BaseOp.getSubReg() == 0);
1235           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1240           .addReg(BaseOp.getReg(), getRegState(BaseOp))
3077   const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3078   if (!BaseOp || !BaseOp->isReg())
3080   BaseOps.push_back(BaseOp);
3316   const MachineOperand &BaseOp = MI.getOperand(BasePos);
3317   if (BaseOp.getSubReg() != 0)
3319   return &const_cast<MachineOperand&>(BaseOp);