Lines Matching +full:sb +full:- +full:rmi
1 //===- HexagonGenInsert.cpp -----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
51 VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden,
53 // The distance cutoff is selected based on the precheckin-perf results:
56 VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden,
62 MaxORLSize("insert-max-orl", cl::init(4096), cl::Hidden,
64 static cl::opt<unsigned> MaxIFMSize("insert-max-ifmap", cl::init(1024),
68 static cl::opt<bool> OptTiming("insert-timing", cl::Hidden,
71 OptTimingDetail("insert-timing-detail", cl::Hidden,
75 static cl::opt<bool> OptSelectAll0("insert-all0", cl::init(false), cl::Hidden);
76 static cl::opt<bool> OptSelectHas0("insert-has0", cl::init(false), cl::Hidden);
79 static cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden);
156 // A.BitVector::test(B) <=> A-B != {}
210 // by a potentially expensive comparison function, or obtained by a proce-
218 return F->second;
231 // - 0 < 1 < ref
232 // - ref1 < ref2, if ord(ref1.Reg) < ord(ref2.Reg),
329 // - the ordering of the register numbers, and
330 // - the ordering of register cells.
332 // - cell(R1) < cell(R2), or
333 // - cell(R1) == cell(R2), and index(R1) < index(R2).
363 // - return false, if at the same time Bit2 exceeds VR2, or
364 // - return true, otherwise.
410 unsigned idx(iterator It) const { return It-begin(); }
563 using IFMapType = DenseMap<unsigned, IFListType>; // vreg -> IFListType
598 if (!CMS->BT.reached(&B))
640 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
652 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
666 // For 32-bit registers, consider: Rd = #s16.
670 // For 64-bit registers, it's Rdd = #s8 or Rdd = combine(#s8,#s8)
676 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
677 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
678 const TargetRegisterClass *InsRC = MRI->getRegClass(InsR);
679 // Only integet (32-/64-bit) register classes.
687 // A 64-bit register can only be generated from other 64-bit registers.
690 // Otherwise, the L and S cannot span 32-bit word boundary.
697 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
707 BitTracker::RegisterCell RC = CMS->lookup(VR);
718 for (const MachineOperand &MO : MI->operands()) {
730 for (const MachineOperand &MO : MI->operands()) {
747 unsigned FromN = FromB->getNumber(), ToN = ToB->getNumber();
751 return F->second;
756 for (const MachineBasicBlock *PB : ToB->predecessors()) {
760 if (PB == FromB || RPO.lookup(PB->getNumber()) >= ToRPO)
762 unsigned D = PB->size() + distance(FromB, PB, RPO, M);
775 const MachineBasicBlock *FB = FromI->getParent(), *TB = ToI->getParent();
778 unsigned D1 = std::distance(TB->begin(), ToI);
780 unsigned D3 = std::distance(FromI, FB->end());
796 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
813 // the corresponding register cells. This means that the range of regis-
819 for (L = 0; L < W-S; ++L) {
839 // Record the final register range. If this range is non-empty, then
840 // L=W-S.
841 assert(B == E || L == W-S);
865 int FDi = -1, LDi = -1; // First/last different bit.
866 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR);
871 if (FDi == -1)
875 if (FDi == -1)
880 uint16_t MinL = LD-FD+1;
885 RSListType &LL = F->second;
890 // given the extra length EL=L-MinL, the prefix must start between
891 // max(0,FD-EL) and FD.
894 uint16_t EL = L-MinL;
895 uint16_t LowS = (EL < FD) ? FD-EL : 0;
923 if (!CMS->BT.reached(B))
941 // Do not collect registers that are known to be compile-time cons-
966 for (auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(B))) {
967 MachineBasicBlock *SB = DTN->getBlock();
968 collectInBlock(SB, AVs);
987 // Breadth-first search.
988 unsigned OtherS = 1-S;
1003 // in case of zero-extending loads, or refs to R.)
1007 const MachineInstr *DefI = MRI->getVRegDef(R);
1012 if (DefI->isPHI())
1018 // The register VR is added to the list as a side-effect of the algorithm,
1021 // IF, and obviously VR (or its replacement) will not become dead by apply-
1040 if (I->second.empty())
1050 IFListType &LL = F->second;
1052 // First, examine the IF candidates for register VR whose removable-regis-
1053 // ter sets are empty. This means that a given candidate will not help eli-
1054 // minate any registers, but since "insert" is not a constant-extendable
1055 // instruction, using such a candidate may reduce code size if the defini-
1056 // tion of VR is constant-extended.
1057 // If there exists a candidate with a non-empty set, the ones with empty
1059 MachineInstr *DefVR = MRI->getVRegDef(VR);
1060 bool DefEx = HII->isConstExtended(*DefVR);
1069 // The definition of VR is not constant-extended, or there is a candidate
1070 // with a non-empty set. Remove all candidates with empty sets.
1071 auto IsEmpty = [] (const IFRecordWithRegSet &IR) -> bool {
1076 // The definition of VR is constant-extended, and all candidates have
1077 // empty removable-register sets. Pick the maximum candidate, and remove
1079 // is only so that the candidate that will remain on the list is selec-
1116 const RegisterSet &RMi = LL[i].second;
1119 if (j != i && LL[j].second.includes(RMi))
1123 if (j == n) { // RMi not contained in anything else.
1136 IFListType &LL = F->second;
1138 const MachineInstr *DefV = MRI->getVRegDef(VR);
1140 for (unsigned i = LL.size(); i > 0; --i) {
1141 unsigned SR = LL[i-1].first.SrcR, IR = LL[i-1].first.InsR;
1142 const MachineInstr *DefS = MRI->getVRegDef(SR);
1143 const MachineInstr *DefI = MRI->getVRegDef(IR);
1150 LL.erase(LL.begin()+(i-1));
1157 IFListType &LL = F->second;
1159 auto IsCopy = [] (const IFRecordWithRegSet &IR) -> bool {
1180 RPO[I->getNumber()] = RPON++;
1197 // First, compare the number of zeros in the associated potentially remova-
1200 // Second, compare "averages", i.e. use-count per size. The lower wins.
1253 unsigned UC = F->second;
1266 // For each potentially removable register R, record the number of regis-
1273 const IFListType &LL = I->second;
1289 use_iterator E = MRI->use_nodbg_end();
1290 for (use_iterator I = MRI->use_nodbg_begin(R); I != E; ++I)
1291 UIs.insert(I->getParent());
1296 UseC[R] = (C > D) ? C-D : 0; // doz
1310 IFListType &LL = I->second;
1314 // element found is adequate, we will put it back on the list, other-
1325 // are the use operands in the definition of I->first. Accept/reject a
1329 const MachineInstr *DefI = MRI->getVRegDef(I->first);
1362 const IFListType &LL = I->second;
1367 IFListType &LL = I->second;
1384 const TargetRegisterClass *RC = MRI->getRegClass(VR);
1385 Register NewVR = MRI->createVirtualRegister(RC);
1389 // We can generate the "insert" instructions using potentially stale re-
1393 MachineInstr *MI = MRI->getVRegDef(I.first);
1394 MachineBasicBlock &B = *MI->getParent();
1395 DebugLoc DL = MI->getDebugLoc();
1397 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
1398 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
1399 : HII->get(Hexagon::S2_insertp);
1403 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
1407 Off -= 32;
1413 if (MI->isPHI())
1422 MRI->clearKillFlags(IF.SrcR);
1423 MRI->clearKillFlags(IF.InsR);
1427 MachineInstr *DefI = MRI->getVRegDef(I.first);
1428 MRI->replaceRegWith(I.first, RegMap[I.first]);
1429 DefI->eraseFromParent();
1441 MachineBasicBlock *B = N->getBlock();
1447 unsigned Opc = MI->getOpcode();
1448 // Do not touch lifetime markers. This is why the target-independent DCE
1454 if (MI->isInlineAsm() || !MI->isSafeToMove(nullptr, Store))
1459 for (const MachineOperand &MO : MI->operands()) {
1463 if (!R.isVirtual() || !MRI->use_nodbg_empty(R)) {
1472 B->erase(MI);
1474 MRI->markUsesInDebugValueAsUndef(Reg);
1507 Changed = removeDeadCode(MDT->getRootNode());
1523 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
1528 MachineBasicBlock *RootB = MDT->getRoot();
1581 unsigned Idx = Register::virtReg2Index(I->first);
1604 //===----------------------------------------------------------------------===//
1606 //===----------------------------------------------------------------------===//