Lines Matching defs:RR
184 bool operator== (RegisterRef RR) const {
185 return Reg == RR.Reg && Sub == RR.Sub;
187 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
188 bool operator< (RegisterRef RR) const {
189 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
204 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
238 bool isIntReg(RegisterRef RR, unsigned &BW);
297 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
299 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
300 ReferenceMap::iterator F = Map.find(RR.Reg);
302 Map.insert(std::make_pair(RR.Reg, Mask));
307 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
309 ReferenceMap::iterator F = Map.find(RR.Reg);
312 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
792 RegisterRef RR = Op;
793 if (RR.Reg == PredR) {
797 if (RR.Reg != RD.Reg)
802 if (RR.Sub == RD.Sub)
804 if (RR.Sub == 0 || RD.Sub == 0)
826 RegisterRef RR = Op;
830 if (!RR.Reg.isVirtual())
833 if (isRefInMap(RR, Defs, Exec_Then))
836 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
1026 RegisterRef RR = Op;
1027 if (!RR.Reg.isVirtual())
1032 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
1036 RR.Sub = 0;
1038 addRefToMap(RR, Map, Exec);
1118 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1119 if (!RR.Reg.isVirtual())
1121 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1127 BW = (RR.Sub != 0) ? 32 : 64;