Lines Matching defs:TR
203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
777 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
803 .addReg(TR, 0, TSR)
816 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
822 TR = RO.getReg(), TSR = RO.getSubReg();
830 if (TR == 0)
831 TR = SR, TSR = SSR;
835 assert(TR || FR);
838 if (TR && FR) {
842 FP.PredR, TR, TSR, FR, FSR);
843 } else if (TR) {
844 MuxR = TR;