Lines Matching defs:FR
204 unsigned TSR, unsigned FR, unsigned FSR);
777 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
804 .addReg(FR, 0, FSR);
816 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
824 FR = RO.getReg(), FSR = RO.getSubReg();
832 else if (FR == 0)
833 FR = SR, FSR = SSR;
835 assert(TR || FR);
838 if (TR && FR) {
842 FP.PredR, TR, TSR, FR, FSR);
847 MuxR = FR;