Lines Matching +full:sense +full:- +full:bitfield +full:- +full:width
1 //===- HexagonConstPropagation.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
55 // of bits make sense, for example Zero and NonZero are mutually exclusive,
102 // Lattice cell, based on that was described in the W-Z paper on constant
201 // Mapping: vreg -> cell
221 // All non-virtual registers are considered "bottom". in has()
233 return F->second; in get()
289 // as well as some helper functions that are target-independent.
298 // - A set of three "evaluate" functions. Each returns "true" if the
307 // If the branch can fall-through, add null (0) to the list of
309 // - A function "rewrite", that given the cell map after propagation,
333 L = 0x04, // Less-than property.
334 G = 0x08, // Greater-than property.
397 bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
399 bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
401 bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
403 bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
414 // Bitfield extract.
415 bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
432 if (CI->isZero()) in deduce()
435 if (CI->isNegative()) in deduce()
442 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero) in deduce()
444 if (CF->isZero()) in deduce()
447 if (CF->isNaN()) in deduce()
449 const APFloat &Val = CF->getValueAPF(); in deduce()
511 C->print(os); in print()
589 // Add a property to the cell. This will force the cell to become a property-
623 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n'; in print()
629 unsigned MBN = MB->getNumber(); in visitPHI()
638 // If the def has a sub-register, set the corresponding cell to "bottom". in visitPHI()
653 unsigned PBN = PB->getNumber(); in visitPHI()
655 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" in visitPHI()
730 // including the potential fall-through to the layout-successor block.
763 if (SB->isEHPad()) in visitBranchesFrom()
787 unsigned TBN = TB->getNumber(); in visitBranchesFrom()
788 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " in visitBranchesFrom()
797 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { in visitUsesOf()
798 // Do not process non-executable instructions. They can become exceutable in visitUsesOf()
799 // later (via a flow-edge in the work queue). In such case, the instruc- in visitUsesOf()
816 MachineBasicBlock::const_iterator FirstBr = MB->end(); in computeBlockSuccessors()
828 MachineBasicBlock::const_iterator End = MB->end(); in computeBlockSuccessors()
844 // If the last branch could fall-through, add block's layout successor. in computeBlockSuccessors()
846 MachineFunction::const_iterator BI = MB->getIterator(); in computeBlockSuccessors()
848 if (NextI != MB->getParent()->end()) in computeBlockSuccessors()
853 for (const MachineBasicBlock *SB : MB->successors()) in computeBlockSuccessors()
854 if (SB->isEHPad()) in computeBlockSuccessors()
863 From->removeSuccessor(To); in removeCFGEdge()
865 for (MachineInstr &PN : To->phis()) { in removeCFGEdge()
867 int N = PN.getNumOperands() - 2; in removeCFGEdge()
873 N -= 2; in removeCFGEdge()
880 unsigned EntryNum = Entry->getNumber(); in propagate()
891 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" in propagate()
900 // - visit all PHI nodes, in propagate()
901 // - visit all non-branch instructions, in propagate()
902 // - visit block branches. in propagate()
903 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end(); in propagate()
906 while (It != End && It->isPHI()) { in propagate()
914 // non-debug instruction to see if it is executable. in propagate()
915 while (It != End && It->isDebugInstr()) in propagate()
917 assert(It == End || !It->isPHI()); in propagate()
921 // For now, scan all non-branch instructions. Branches require different in propagate()
923 while (It != End && !It->isBranch()) { in propagate()
924 if (!It->isDebugInstr()) { in propagate()
932 // processing regular (non-branch) instructions, because there can in propagate()
940 unsigned SBN = SB->getNumber(); in propagate()
941 for (const MachineBasicBlock *SSB : SB->successors()) in propagate()
942 FlowQ.push(CFGEdge(SBN, SSB->getNumber())); in propagate()
953 unsigned SN = SB->getNumber(); in propagate()
955 dbgs() << " " << printMBBReference(B) << " -> " in propagate()
966 // Traverse the instructions in a post-order, so that rewriting an in rewrite()
967 // instruction can make changes "downstream" in terms of control-flow in rewrite()
977 // Collect the post-order-traversal block ordering. The subsequent in rewrite()
982 if (!B->empty()) in rewrite()
1004 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing in rewrite()
1007 for (auto I = B->begin(), E = B->end(); I != E; ++I) { in rewrite()
1008 if (I->isPHI()) in rewrite()
1013 if (P->isPHI()) in rewrite()
1019 B->splice(I, B, P); in rewrite()
1021 --I; in rewrite()
1026 for (MachineBasicBlock *SB : B->successors()) { in rewrite()
1035 // This could legitimately happen in blocks that have non-returning in rewrite()
1036 // calls---we would think that the execution can continue, but the in rewrite()
1040 // Need to do some final post-processing. in rewrite()
1053 // This is the constant propagation algorithm as described by Wegman-Zadeck.
1076 // --------------------------------------------------------------------
1097 Val = CI->getValue(); in constToInt()
1327 // or a known non-zero. in evaluateCMPpp()
1375 // with the non-bottom argument passed as the immediate. This is to in evaluateANDrr()
1403 if (A2 == -1) in evaluateANDri()
1442 // with the non-bottom argument passed as the immediate. This is to in evaluateORrr()
1443 // catch cases of ORing with -1. in evaluateORrr()
1472 if (A2 == -1) { in evaluateORri()
1565 bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, in evaluateZEXTr() argument
1577 evaluateZEXTi(A, Width, Bits, XA); in evaluateZEXTr()
1586 bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width, in evaluateZEXTi() argument
1590 assert(Width >= Bits && BW >= Bits); in evaluateZEXTi()
1591 APInt Mask = APInt::getLowBitsSet(Width, Bits); in evaluateZEXTi()
1592 Result = A1.zextOrTrunc(Width) & Mask; in evaluateZEXTi()
1596 bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, in evaluateSEXTr() argument
1608 evaluateSEXTi(A, Width, Bits, XA); in evaluateSEXTr()
1617 bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width, in evaluateSEXTi() argument
1620 assert(Width >= Bits && BW >= Bits); in evaluateSEXTi()
1625 Result = APInt(Width, 0); in evaluateSEXTi()
1645 V = (V << (64-Bits)) >> (64-Bits); in evaluateSEXTi()
1648 // V is a 64-bit sign-extended value. Convert it to APInt of desired in evaluateSEXTi()
1649 // width. in evaluateSEXTi()
1650 Result = APInt(Width, V, true); in evaluateSEXTi()
1655 Result = A1.trunc(Bits).sext(Width); in evaluateSEXTi()
1657 Result = A1.sext(Width); in evaluateSEXTi()
1732 unsigned Width, unsigned Bits, unsigned Offset, bool Signed, in evaluateEXTRACTr() argument
1735 assert(Bits+Offset <= Width); in evaluateEXTRACTr()
1744 const Constant *C = intToConst(APInt(Width, 0, false)); in evaluateEXTRACTr()
1774 V <<= (64-Bits-Offset); in evaluateEXTRACTi()
1776 V >>= (64-Bits); in evaluateEXTRACTi()
1778 V = static_cast<uint64_t>(V) >> (64-Bits); in evaluateEXTRACTi()
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits); in evaluateEXTRACTi()
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits); in evaluateEXTRACTi()
1828 // ----------------------------------------------------------------------
1829 // Hexagon-specific code.
1865 // This is suitable to be called for compare-and-jump instructions.
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate()
2097 // All of these instructions return a 32-bit value. The evaluate in evaluate()
2129 // All of these instructions return a 32-bit value. The evaluate in evaluate()
2162 // If the requested bitfield extends beyond the most significant bit, in evaluate()
2165 Bits = BW-Offset; in evaluate()
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); in evaluate()
2351 // a register that is not compile-time constant), then try to rewrite in rewrite()
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in getRegBitWidth()
2582 // Only create a zero/non-zero cell. At this time there isn't really in evaluateHexCompare()
2832 // Avoid generating TFRIs for register transfers---this will keep the in rewriteHexConstDefs()
2837 MachineFunction *MF = MI.getParent()->getParent(); in rewriteHexConstDefs()
2838 auto &HST = MF->getSubtarget<HexagonSubtarget>(); in rewriteHexConstDefs()
2840 // Collect all virtual register-def operands. in rewriteHexConstDefs()
2867 const TargetRegisterClass *RC = MRI->getRegClass(R); in rewriteHexConstDefs()
2871 // If this a zero/non-zero cell, we can fold a definition in rewriteHexConstDefs()
2884 Register NewR = MRI->createVirtualRegister(PredRC); in rewriteHexConstDefs()
2906 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
2926 } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) { in rewriteHexConstDefs()
2946 MachineFunction &MF = *MI.getParent()->getParent(); in rewriteHexConstDefs()
2971 // or DefR -= mpyi(R, #imm). in rewriteHexConstUses()
2980 // to replace one argument---whichever happens to be a single constant. in rewriteHexConstUses()
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
2995 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3000 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3022 V = -V; in rewriteHexConstUses()
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3024 Register NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3042 // Check if any of the operands is -1 (i.e. all bits set). in rewriteHexConstUses()
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3061 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3066 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3093 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3098 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3106 for (MachineOperand &MO : NewMI->operands()) in rewriteHexConstUses()
3129 llvm::make_early_inc_range(MRI->use_operands(FromReg))) in replaceAllRegUsesWith()
3153 // MIB.addMBB needs non-const pointer. in rewriteHexBranch()
3158 // erased as "non-executable". We can't mark any new instructions in rewriteHexBranch()
3167 // This ensures that all implicit operands (e.g. implicit-def %r31, etc) in rewriteHexBranch()
3169 for (auto &Op : NI->operands()) in rewriteHexBranch()
3171 NI->eraseFromParent(); in rewriteHexBranch()