Lines Matching +full:all +full:- +full:inputs +full:- +full:2
1 //===- HexagonConstPropagation.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
54 // value is known (proven) to have this property. Not all combinations
102 // Lattice cell, based on that was described in the W-Z paper on constant
107 // could be folded if all the values in the cell associated with X are
115 unsigned Kind:2;
201 // Mapping: vreg -> cell
221 // All non-virtual registers are considered "bottom". in has()
233 return F->second; in get()
289 // as well as some helper functions that are target-independent.
298 // - A set of three "evaluate" functions. Each returns "true" if the
300 // (1) Given an instruction MI, and the map with input values "Inputs",
304 // (2) Given a register R (as reg:subreg), compute the cell that
307 // If the branch can fall-through, add null (0) to the list of
309 // - A function "rewrite", that given the cell map after propagation,
313 virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
317 virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
320 virtual bool rewrite(MachineInstr &MI, const CellMap &Inputs) = 0;
333 L = 0x04, // Less-than property.
334 G = 0x08, // Greater-than property.
358 bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
364 const CellMap &Inputs, bool &Result);
366 const CellMap &Inputs, bool &Result);
368 const CellMap &Inputs, bool &Result);
376 bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
381 const CellMap &Inputs, LatticeCell &Result);
383 const CellMap &Inputs, LatticeCell &Result);
386 const CellMap &Inputs, LatticeCell &Result);
388 const CellMap &Inputs, LatticeCell &Result);
391 const CellMap &Inputs, LatticeCell &Result);
393 const CellMap &Inputs, LatticeCell &Result);
398 const CellMap &Inputs, LatticeCell &Result);
402 const CellMap &Inputs, LatticeCell &Result);
408 const CellMap &Inputs, LatticeCell &Result);
411 const CellMap &Inputs, LatticeCell &Result);
416 unsigned Offset, bool Signed, const CellMap &Inputs,
422 const CellMap &Inputs, LatticeCell &Result);
432 if (CI->isZero()) in deduce()
435 if (CI->isNegative()) in deduce()
442 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero) in deduce()
444 if (CF->isZero()) in deduce()
447 if (CF->isNaN()) in deduce()
449 const APFloat &Val = CF->getValueAPF(); in deduce()
511 C->print(os); in print()
589 // Add a property to the cell. This will force the cell to become a property-
623 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n'; in print()
629 unsigned MBN = MB->getNumber(); in visitPHI()
638 // If the def has a sub-register, set the corresponding cell to "bottom". in visitPHI()
651 for (unsigned i = 1, n = PN.getNumOperands(); i < n; i += 2) { in visitPHI()
653 unsigned PBN = PB->getNumber(); in visitPHI()
655 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" in visitPHI()
698 // Update outputs. If the value was not computed, set all the in visitNonBranch()
708 // If the evaluation failed, set cells for all output registers to bottom. in visitNonBranch()
729 // can fall through. Add all the possible targets to the flow work queue,
730 // including the potential fall-through to the layout-successor block.
759 // Need to add all CFG successors that lead to EH landing pads. in visitBranchesFrom()
763 if (SB->isEHPad()) in visitBranchesFrom()
775 // set of all successors of the block from the CFG. in visitBranchesFrom()
776 // If the evaluation succeeded for all visited branches, then if the in visitBranchesFrom()
780 LLVM_DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG " in visitBranchesFrom()
787 unsigned TBN = TB->getNumber(); in visitBranchesFrom()
788 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " in visitBranchesFrom()
797 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { in visitUsesOf()
798 // Do not process non-executable instructions. They can become exceutable in visitUsesOf()
799 // later (via a flow-edge in the work queue). In such case, the instruc- in visitUsesOf()
816 MachineBasicBlock::const_iterator FirstBr = MB->end(); in computeBlockSuccessors()
828 MachineBasicBlock::const_iterator End = MB->end(); in computeBlockSuccessors()
844 // If the last branch could fall-through, add block's layout successor. in computeBlockSuccessors()
846 MachineFunction::const_iterator BI = MB->getIterator(); in computeBlockSuccessors()
848 if (NextI != MB->getParent()->end()) in computeBlockSuccessors()
852 // Add all the EH landing pads. in computeBlockSuccessors()
853 for (const MachineBasicBlock *SB : MB->successors()) in computeBlockSuccessors()
854 if (SB->isEHPad()) in computeBlockSuccessors()
863 From->removeSuccessor(To); in removeCFGEdge()
864 // Remove all corresponding PHI operands in the To block. in removeCFGEdge()
865 for (MachineInstr &PN : To->phis()) { in removeCFGEdge()
867 int N = PN.getNumOperands() - 2; in removeCFGEdge()
873 N -= 2; in removeCFGEdge()
880 unsigned EntryNum = Entry->getNumber(); in propagate()
891 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" in propagate()
900 // - visit all PHI nodes, in propagate()
901 // - visit all non-branch instructions, in propagate()
902 // - visit block branches. in propagate()
903 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end(); in propagate()
906 while (It != End && It->isPHI()) { in propagate()
912 // If the successor block just became executable, visit all instructions. in propagate()
914 // non-debug instruction to see if it is executable. in propagate()
915 while (It != End && It->isDebugInstr()) in propagate()
917 assert(It == End || !It->isPHI()); in propagate()
921 // For now, scan all non-branch instructions. Branches require different in propagate()
923 while (It != End && !It->isBranch()) { in propagate()
924 if (!It->isDebugInstr()) { in propagate()
932 // processing regular (non-branch) instructions, because there can in propagate()
938 // If the block didn't have a branch, add all successor edges to the in propagate()
940 unsigned SBN = SB->getNumber(); in propagate()
941 for (const MachineBasicBlock *SSB : SB->successors()) in propagate()
942 FlowQ.push(CFGEdge(SBN, SSB->getNumber())); in propagate()
953 unsigned SN = SB->getNumber(); in propagate()
955 dbgs() << " " << printMBBReference(B) << " -> " in propagate()
964 // Rewrite all instructions based on the collected cell information. in rewrite()
966 // Traverse the instructions in a post-order, so that rewriting an in rewrite()
967 // instruction can make changes "downstream" in terms of control-flow in rewrite()
977 // Collect the post-order-traversal block ordering. The subsequent in rewrite()
982 if (!B->empty()) in rewrite()
1004 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing in rewrite()
1005 // regular instructions to appear in between PHI nodes. Bring all in rewrite()
1007 for (auto I = B->begin(), E = B->end(); I != E; ++I) { in rewrite()
1008 if (I->isPHI()) in rewrite()
1013 if (P->isPHI()) in rewrite()
1019 B->splice(I, B, P); in rewrite()
1021 --I; in rewrite()
1025 SmallVector<MachineBasicBlock*,2> ToRemove; in rewrite()
1026 for (MachineBasicBlock *SB : B->successors()) { in rewrite()
1035 // This could legitimately happen in blocks that have non-returning in rewrite()
1036 // calls---we would think that the execution can continue, but the in rewrite()
1040 // Need to do some final post-processing. in rewrite()
1053 // This is the constant propagation algorithm as described by Wegman-Zadeck.
1076 // --------------------------------------------------------------------
1079 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs, in getCell() argument
1083 const LatticeCell &L = Inputs.get(R.Reg); in getCell()
1097 Val = CI->getValue(); in constToInt()
1106 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) { in evaluateCMPrr() argument
1107 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in evaluateCMPrr()
1109 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) in evaluateCMPrr()
1119 return evaluateCMPrp(NegCmp, R2, Prop1, Inputs, Result); in evaluateCMPrr()
1123 return evaluateCMPrp(Cmp, R1, Prop2, Inputs, Result); in evaluateCMPrr()
1131 evaluateCMPri(Cmp, R1, A, Inputs, Res); in evaluateCMPrr()
1145 const APInt &A2, const CellMap &Inputs, bool &Result) { in evaluateCMPri() argument
1146 assert(Inputs.has(R1.Reg)); in evaluateCMPri()
1148 if (!getCell(R1, Inputs, LS)) in evaluateCMPri()
1172 uint64_t Props2, const CellMap &Inputs, bool &Result) { in evaluateCMPrp() argument
1173 assert(Inputs.has(R1.Reg)); in evaluateCMPrp()
1175 if (!getCell(R1, Inputs, LS)) in evaluateCMPrp()
1327 // or a known non-zero. in evaluateCMPpp()
1365 const CellMap &Inputs, LatticeCell &Result) { in evaluateCOPY() argument
1366 return getCell(R1, Inputs, Result); in evaluateCOPY()
1370 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDrr() argument
1371 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in evaluateANDrr()
1372 const LatticeCell &L1 = Inputs.get(R2.Reg); in evaluateANDrr()
1373 const LatticeCell &L2 = Inputs.get(R2.Reg); in evaluateANDrr()
1375 // with the non-bottom argument passed as the immediate. This is to in evaluateANDrr()
1380 return evaluateANDrr(R2, R1, Inputs, Result); in evaluateANDrr()
1392 evaluateANDri(R1, A, Inputs, RC); in evaluateANDrr()
1401 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateANDri() argument
1402 assert(Inputs.has(R1.Reg)); in evaluateANDri()
1403 if (A2 == -1) in evaluateANDri()
1404 return getCell(R1, Inputs, Result); in evaluateANDri()
1413 if (!getCell(R1, Inputs, LS1)) in evaluateANDri()
1437 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORrr() argument
1438 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in evaluateORrr()
1439 const LatticeCell &L1 = Inputs.get(R2.Reg); in evaluateORrr()
1440 const LatticeCell &L2 = Inputs.get(R2.Reg); in evaluateORrr()
1442 // with the non-bottom argument passed as the immediate. This is to in evaluateORrr()
1443 // catch cases of ORing with -1. in evaluateORrr()
1447 return evaluateORrr(R2, R1, Inputs, Result); in evaluateORrr()
1459 evaluateORri(R1, A, Inputs, RC); in evaluateORrr()
1468 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateORri() argument
1469 assert(Inputs.has(R1.Reg)); in evaluateORri()
1471 return getCell(R1, Inputs, Result); in evaluateORri()
1472 if (A2 == -1) { in evaluateORri()
1480 if (!getCell(R1, Inputs, LS1)) in evaluateORri()
1504 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORrr() argument
1505 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in evaluateXORrr()
1507 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) in evaluateXORrr()
1524 evaluateXORri(R1, A, Inputs, RC); in evaluateXORrr()
1533 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) { in evaluateXORri() argument
1534 assert(Inputs.has(R1.Reg)); in evaluateXORri()
1536 if (!getCell(R1, Inputs, LS1)) in evaluateXORri()
1566 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) { in evaluateZEXTr() argument
1567 assert(Inputs.has(R1.Reg)); in evaluateZEXTr()
1569 if (!getCell(R1, Inputs, LS1)) in evaluateZEXTr()
1597 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) { in evaluateSEXTr() argument
1598 assert(Inputs.has(R1.Reg)); in evaluateSEXTr()
1600 if (!getCell(R1, Inputs, LS1)) in evaluateSEXTr()
1642 // Shift left to lose all bits except lower "Bits" bits, then shift in evaluateSEXTi()
1645 V = (V << (64-Bits)) >> (64-Bits); in evaluateSEXTi()
1648 // V is a 64-bit sign-extended value. Convert it to APInt of desired in evaluateSEXTi()
1662 bool Ones, const CellMap &Inputs, LatticeCell &Result) { in evaluateCLBr() argument
1663 assert(Inputs.has(R1.Reg)); in evaluateCLBr()
1665 if (!getCell(R1, Inputs, LS1)) in evaluateCLBr()
1697 bool Ones, const CellMap &Inputs, LatticeCell &Result) { in evaluateCTBr() argument
1698 assert(Inputs.has(R1.Reg)); in evaluateCTBr()
1700 if (!getCell(R1, Inputs, LS1)) in evaluateCTBr()
1733 const CellMap &Inputs, LatticeCell &Result) { in evaluateEXTRACTr() argument
1734 assert(Inputs.has(R1.Reg)); in evaluateEXTRACTr()
1737 if (!getCell(R1, Inputs, LS1)) in evaluateEXTRACTr()
1774 V <<= (64-Bits-Offset); in evaluateEXTRACTi()
1776 V >>= (64-Bits); in evaluateEXTRACTi()
1778 V = static_cast<uint64_t>(V) >> (64-Bits); in evaluateEXTRACTi()
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits); in evaluateEXTRACTi()
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits); in evaluateEXTRACTi()
1790 unsigned Bits, unsigned Count, const CellMap &Inputs, in evaluateSplatr() argument
1792 assert(Inputs.has(R1.Reg)); in evaluateSplatr()
1794 if (!getCell(R1, Inputs, LS1)) in evaluateSplatr()
1828 // ----------------------------------------------------------------------
1829 // Hexagon-specific code.
1844 bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
1848 bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
1851 bool rewrite(MachineInstr &MI, const CellMap &Inputs) override;
1861 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
1863 bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
1865 // This is suitable to be called for compare-and-jump instructions.
1867 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
1868 bool evaluateHexLogical(const MachineInstr &MI, const CellMap &Inputs,
1870 bool evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs,
1872 bool evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs,
1874 bool evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs,
1876 bool evaluateHexVector2(const MachineInstr &MI, const CellMap &Inputs,
1880 bool rewriteHexBranch(MachineInstr &BrI, const CellMap &Inputs);
1881 bool rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs,
1883 bool rewriteHexConstUses(MachineInstr &MI, const CellMap &Inputs);
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1925 const CellMap &Inputs, CellMap &Outputs) { in evaluate() argument
1943 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
1950 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate()
1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate()
1965 bool Eval = evaluateHexRSEQ32(SrcRL, SrcRH, Inputs, RC); in evaluate()
1972 bool Eval = evaluateHexCompare(MI, Inputs, Outputs); in evaluate()
1987 // Do this check for all instructions for safety. in evaluate()
2024 bool Eval = evaluateHexLogical(MI, Inputs, Outputs); in evaluate()
2033 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm()) in evaluate()
2036 uint64_t Lo = MI.getOperand(2).getImm(); in evaluate()
2048 int64_t B = MI.getOperand(2).getImm(); in evaluate()
2053 bool Eval = evaluateORri(R, A, Inputs, RC); in evaluate()
2065 bool Eval = evaluateHexCondMove(MI, Inputs, Outputs); in evaluate()
2077 bool Eval = evaluateHexExt(MI, Inputs, Outputs); in evaluate()
2092 assert(Inputs.has(R1.Reg)); in evaluate()
2094 bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T); in evaluate()
2097 // All of these instructions return a 32-bit value. The evaluate in evaluate()
2124 assert(Inputs.has(R1.Reg)); in evaluate()
2126 bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T); in evaluate()
2129 // All of these instructions return a 32-bit value. The evaluate in evaluate()
2153 unsigned Bits = MI.getOperand(2).getImm(); in evaluate()
2165 Bits = BW-Offset; in evaluate()
2168 bool Eval = evaluateEXTRACTr(R1, BW, Bits, Offset, Signed, Inputs, RC); in evaluate()
2186 bool Eval = evaluateHexVector1(MI, Inputs, Outputs); in evaluate()
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); in evaluate()
2259 const CellMap &Inputs, SetVector<const MachineBasicBlock*> &Targets, in evaluate() argument
2262 // all the branches in a basic block at once, so we cannot use it. in evaluate()
2285 // If the branch is of unknown type, assume that all successors are in evaluate()
2298 assert(Inputs.has(PR.Reg)); in evaluate()
2299 const LatticeCell &PredC = Inputs.get(PR.Reg); in evaluate()
2327 bool HexagonConstEvaluator::rewrite(MachineInstr &MI, const CellMap &Inputs) { in rewrite() argument
2329 return rewriteHexBranch(MI, Inputs); in rewrite()
2349 Changed = rewriteHexConstDefs(MI, Inputs, AllDefs); in rewrite()
2350 // If not all defs have been rewritten (i.e. the instruction defines in rewrite()
2351 // a register that is not compile-time constant), then try to rewrite in rewrite()
2354 Changed |= rewriteHexConstUses(MI, Inputs); in rewrite()
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in getRegBitWidth()
2516 const CellMap &Inputs, LatticeCell &Result) { in evaluateHexRSEQ32() argument
2517 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); in evaluateHexRSEQ32()
2519 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
2553 const CellMap &Inputs, CellMap &Outputs) { in evaluateHexCompare() argument
2576 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexCompare()
2580 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result); in evaluateHexCompare()
2582 // Only create a zero/non-zero cell. At this time there isn't really in evaluateHexCompare()
2599 const CellMap &Inputs, bool &Result) { in evaluateHexCompare2() argument
2607 return evaluateCMPrr(Cmp, R1, R2, Inputs, Result); in evaluateHexCompare2()
2609 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2610 return evaluateCMPri(Cmp, R1, A2, Inputs, Result); in evaluateHexCompare2()
2617 return evaluateCMPri(NegCmp, R2, A1, Inputs, Result); in evaluateHexCompare2()
2619 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2628 const CellMap &Inputs, CellMap &Outputs) { in evaluateHexLogical() argument
2633 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexLogical()
2642 Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC); in evaluateHexLogical()
2648 Eval = evaluateANDri(R1, A, Inputs, RC); in evaluateHexLogical()
2653 Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC); in evaluateHexLogical()
2659 Eval = evaluateORri(R1, A, Inputs, RC); in evaluateHexLogical()
2664 Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC); in evaluateHexLogical()
2675 const CellMap &Inputs, CellMap &Outputs) { in evaluateHexCondMove() argument
2678 assert(Inputs.has(CR.Reg)); in evaluateHexCondMove()
2680 if (!getCell(CR, Inputs, LS)) in evaluateHexCondMove()
2687 TakeOp = 2; in evaluateHexCondMove()
2706 const LatticeCell &LR = Inputs.get(R.Reg); in evaluateHexCondMove()
2718 const CellMap &Inputs, CellMap &Outputs) { in evaluateHexExt() argument
2721 assert(Inputs.has(R1.Reg)); in evaluateHexExt()
2753 bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC) in evaluateHexExt()
2754 : evaluateZEXTr(R1, BW, Bits, Inputs, RC); in evaluateHexExt()
2762 const CellMap &Inputs, CellMap &Outputs) { in evaluateHexVector1() argument
2766 assert(Inputs.has(R1.Reg)); in evaluateHexVector1()
2774 Eval = evaluateSplatr(R1, 8, 4, Inputs, RC); in evaluateHexVector1()
2778 Eval = evaluateSplatr(R1, 16, 4, Inputs, RC); in evaluateHexVector1()
2791 const CellMap &Inputs, bool &AllDefs) { in rewriteHexConstDefs() argument
2795 // LLVM_DEBUG({...}) gets confused with all this code as an argument. in rewriteHexConstDefs()
2808 if (!MI.isPHI() && !Inputs.has(R.Reg)) { in rewriteHexConstDefs()
2813 const LatticeCell &L = Inputs.get(R.Reg); in rewriteHexConstDefs()
2825 dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; in rewriteHexConstDefs()
2832 // Avoid generating TFRIs for register transfers---this will keep the in rewriteHexConstDefs()
2837 MachineFunction *MF = MI.getParent()->getParent(); in rewriteHexConstDefs()
2838 auto &HST = MF->getSubtarget<HexagonSubtarget>(); in rewriteHexConstDefs()
2840 // Collect all virtual register-def operands. in rewriteHexConstDefs()
2841 SmallVector<unsigned,2> DefRegs; in rewriteHexConstDefs()
2849 assert(Inputs.has(R)); in rewriteHexConstDefs()
2862 // and replace all uses of the defined register with NewR. in rewriteHexConstDefs()
2864 const LatticeCell &L = Inputs.get(R); in rewriteHexConstDefs()
2867 const TargetRegisterClass *RC = MRI->getRegClass(R); in rewriteHexConstDefs()
2871 // If this a zero/non-zero cell, we can fold a definition in rewriteHexConstDefs()
2884 Register NewR = MRI->createVirtualRegister(PredRC); in rewriteHexConstDefs()
2906 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
2926 } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) { in rewriteHexConstDefs()
2946 MachineFunction &MF = *MI.getParent()->getParent(); in rewriteHexConstDefs()
2959 const CellMap &Inputs) { in rewriteHexConstUses() argument
2971 // or DefR -= mpyi(R, #imm). in rewriteHexConstUses()
2975 RegisterSubReg R2(MI.getOperand(2)); in rewriteHexConstUses()
2977 assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg)); in rewriteHexConstUses()
2980 // to replace one argument---whichever happens to be a single constant. in rewriteHexConstUses()
2981 bool HasC2 = getCell(R2, Inputs, LS2), HasC3 = getCell(R3, Inputs, LS3); in rewriteHexConstUses()
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
2995 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3000 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3013 : MI.getOperand(2); in rewriteHexConstUses()
3022 V = -V; in rewriteHexConstUses()
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3024 Register NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3038 RegisterSubReg R2(MI.getOperand(2)); in rewriteHexConstUses()
3039 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in rewriteHexConstUses()
3042 // Check if any of the operands is -1 (i.e. all bits set). in rewriteHexConstUses()
3043 if (getCell(R1, Inputs, LS1) && LS1.isSingle()) { in rewriteHexConstUses()
3046 CopyOf = 2; in rewriteHexConstUses()
3048 else if (getCell(R2, Inputs, LS2) && LS2.isSingle()) { in rewriteHexConstUses()
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3061 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3066 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3074 RegisterSubReg R2(MI.getOperand(2)); in rewriteHexConstUses()
3075 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg)); in rewriteHexConstUses()
3081 if (getCell(R1, Inputs, LS1) && (LS1.properties() & P::Zero)) in rewriteHexConstUses()
3082 CopyOf = 2; in rewriteHexConstUses()
3083 else if (getCell(R2, Inputs, LS2) && (LS2.properties() & P::Zero)) in rewriteHexConstUses()
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); in rewriteHexConstUses()
3093 NewR = MRI->createVirtualRegister(RC); in rewriteHexConstUses()
3098 MRI->clearKillFlags(NewR); in rewriteHexConstUses()
3105 // clear all the kill flags of this new instruction. in rewriteHexConstUses()
3106 for (MachineOperand &MO : NewMI->operands()) in rewriteHexConstUses()
3129 llvm::make_early_inc_range(MRI->use_operands(FromReg))) in replaceAllRegUsesWith()
3134 const CellMap &Inputs) { in rewriteHexBranch() argument
3142 bool Eval = evaluate(BrI, Inputs, Targets, FallsThru); in rewriteHexBranch()
3153 // MIB.addMBB needs non-const pointer. in rewriteHexBranch()
3158 // erased as "non-executable". We can't mark any new instructions in rewriteHexBranch()
3167 // This ensures that all implicit operands (e.g. implicit-def %r31, etc) in rewriteHexBranch()
3169 for (auto &Op : NI->operands()) in rewriteHexBranch()
3171 NI->eraseFromParent(); in rewriteHexBranch()