Lines Matching defs:Opc
249 static bool getUsedBitsInStore(unsigned Opc, BitVector &Bits,
251 static bool getUsedBits(unsigned Opc, unsigned OpN, BitVector &Bits,
492 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits,
496 switch (Opc) {
643 // For an instruction with opcode Opc, calculate the set of bits that it
651 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN,
655 const MCInstrDesc &D = HII.get(Opc);
658 return getUsedBitsInStore(Opc, Bits, Begin);
662 switch (Opc) {
1030 unsigned Opc = MI->getOpcode();
1033 if (Opc == TargetOpcode::LIFETIME_START ||
1034 Opc == TargetOpcode::LIFETIME_END)
1112 unsigned Opc = MI.getOpcode();
1114 switch (Opc) {
1172 unsigned Opc = MI.getOpcode();
1174 switch (Opc) {
1280 unsigned Opc = MI.getOpcode();
1282 bool GotBits = HBS::getUsedBits(Opc, OpN, T, Begin, HII);
1423 unsigned Opc = MI.getOpcode();
1424 switch (Opc) {
1460 unsigned Opc = isInt<8>(Lo) ? Hexagon::A2_combineii
1462 BuildMI(B, At, DL, HII.get(Opc), Reg)
1480 unsigned Opc;
1482 Opc = Hexagon::PS_false;
1484 Opc = Hexagon::PS_true;
1487 BuildMI(B, At, DL, HII.get(Opc), Reg);
1560 static bool isCopyReg(unsigned Opc, bool NoConv);
1632 unsigned Opc = I->getOpcode();
1633 if (CopyPropagation::isCopyReg(Opc, false) ||
1681 bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
1682 switch (Opc) {
1701 unsigned Opc = MI.getOpcode();
1705 switch (Opc) {
1741 unsigned SrcX = (Opc == Hexagon::A4_combineir) ? 2 : 1;
1742 unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::isub_lo
1759 unsigned Opc = I->getOpcode();
1760 if (!CopyPropagation::isCopyReg(Opc, true))
1790 bool validateReg(BitTracker::RegisterRef R, unsigned Opc, unsigned OpNum);
1909 bool BitSimplification::validateReg(BitTracker::RegisterRef R, unsigned Opc,
1911 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);
1950 unsigned Opc = MI->getOpcode();
1951 if (Opc != Hexagon::S2_storerh_io)
1974 unsigned Opc = MI->getOpcode();
1976 switch (Opc) {
2011 switch (Opc) {
2022 // Opc is already checked above to be one of the three store instructions.
2030 switch (Opc) {
2051 unsigned Opc = MI->getOpcode();
2052 if (Opc == Hexagon::S2_packhl)
2083 unsigned Opc = MI->getOpcode();
2092 if (L.Low && Opc != Hexagon::A2_zxth) {
2098 } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
2125 unsigned Opc = MI->getOpcode();
2127 if (COpc == Opc)
2149 unsigned Opc = MI->getOpcode();
2150 switch (Opc) {
2156 if (Opc == Hexagon::A2_andir && MI->getOperand(2).isImm()) {
2217 unsigned Opc = MI->getOpcode();
2218 switch (Opc) {
2362 unsigned Opc = MI->getOpcode();
2363 if (Opc != Hexagon::S2_tstbit_i)
2614 unsigned Opc = MI->getOpcode();
2615 if (Opc != Hexagon::A4_rcmpeqi && Opc != Hexagon::A4_rcmpneqi)
2691 return ReplaceWithConst(KnownZ == (Opc == Hexagon::A4_rcmpeqi));
2705 return ReplaceWithConst(Opc == Hexagon::A4_rcmpneqi);
2709 return ReplaceWithConst(Opc == Hexagon::A4_rcmpeqi);
2718 .addImm(KnownZ1 == (Opc == Hexagon::A4_rcmpeqi))
2719 .addImm(KnownZ2 == (Opc == Hexagon::A4_rcmpeqi));
2746 unsigned Opc = MI->getOpcode();
2747 if (Opc == TargetOpcode::COPY || Opc == TargetOpcode::REG_SEQUENCE)
3017 unsigned Opc = MI->getOpcode();
3018 switch (Opc) {
3308 unsigned Opc = DefPrehR->getOpcode();
3309 if (Opc != Hexagon::A2_tfrsi && Opc != Hexagon::A2_tfrpi)