Lines Matching +full:mii +full:- +full:rt
1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
13 //===----------------------------------------------------------------------===//
65 #define DEBUG_TYPE "asm-printer"
71 unsigned Pair = *RI->superregs(Reg).begin();
78 const MachineOperand &MO = MI->getOperand(OpNo);
90 MO.getMBB()->getSymbol()->print(O, MAI);
93 GetCPISymbol(MO.getIndex())->print(O, MAI);
101 // isBlockOnlyReachableByFallthrough - We need to override this since the
109 if (MBB->hasAddressTaken())
114 /// PrintAsmOperand - Print out an operand for an inline asm expression.
128 case 'H': { // The highest-numbered register of a pair.
129 const MachineOperand &MO = MI->getOperand(OpNo);
130 const MachineFunction &MF = *MI->getParent()->getParent();
137 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
146 if (MI->getOperand(OpNo).isImm())
163 const MachineOperand &Base = MI->getOperand(OpNo);
164 const MachineOperand &Offset = MI->getOperand(OpNo+1);
186 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
209 if (Sym->isUndefined()) {
229 StringRef SymbolName = MOSymbol->getName();
237 if (Sym->isUndefined()) {
258 int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
269 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
270 const MachineFunction &MF = *MI.getParent()->getParent();
328 if (!OutStreamer->hasRawTextSupport()) {
330 MCSectionSubPair Current = OutStreamer->getCurrentSection();
335 OutStreamer->switchSection(Current.first, Current.second);
347 if (!OutStreamer->hasRawTextSupport()) {
349 MCSectionSubPair Current = OutStreamer->getCurrentSection();
352 OutStreamer->switchSection(Current.first, Current.second);
373 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
377 MCOperand &Rt = Inst.getOperand(3);
378 assert(Rt.isReg() && "Expected register and none was found");
379 unsigned Reg = RI->getEncodingValue(Rt.getReg());
384 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
388 MCOperand &Rt = Inst.getOperand(2);
389 assert(Rt.isReg() && "Expected register and none was found");
390 unsigned Reg = RI->getEncodingValue(Rt.getReg());
395 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
400 MCOperand &Rt = Inst.getOperand(2);
401 assert(Rt.isReg() && "Expected register and none was found");
402 unsigned Reg = RI->getEncodingValue(Rt.getReg());
407 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
414 unsigned Reg = RI->getEncodingValue(Rs.getReg());
415 if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
431 bool Success = Expr->evaluateAsAbsolute(Imm);
458 bool Success = Expr->evaluateAsAbsolute(Imm);
466 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
467 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
489 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
494 bool Success = Expr->evaluateAsAbsolute(Imm);
516 // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
525 bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
527 const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
540 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
543 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
544 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
555 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
556 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
569 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
570 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
584 bool Success = Expr->evaluateAsAbsolute(Value);
587 if (Value < 0 && Value > -256) {
597 MCOperand &Rt = Inst.getOperand(1);
598 assert(Rt.isReg() && "Expected register and none was found");
599 unsigned Reg = RI->getEncodingValue(Rt.getReg());
604 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
747 Hexagon_MC::verifyInstructionPredicates(MI->getOpcode(),
753 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
755 if (MI->isBundle()) {
756 const MachineBasicBlock* MBB = MI->getParent();
757 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
759 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
760 if (!MII->isDebugInstr() && !MII->isImplicitDef())
761 HexagonLowerToMC(MCII, &*MII, MCB, *this);
766 const MachineFunction &MF = *MI->getParent()->getParent();
768 if (MI->isBundle() && HII.getBundleNoShuf(*MI))
771 MCContext &Ctx = OutStreamer->getContext();
777 OutStreamer->emitInstruction(MCB, getSubtargetInfo());
787 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
794 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
815 // { immext(#...) // upper 26-bits of trampoline
816 // r6 = ##... // lower 6-bits of trampoline
817 // immext(#...) // upper 26-bits of func id
823 OutStreamer->emitLabel(CurSled);
826 SledJump->setOpcode(Hexagon::J2_jump);
828 SledJump->addOperand(MCOperand::createExpr(HexagonMCExpr::create(
840 // special-case this and combine them into a single packet.
843 OutStreamer->emitLabel(PostSled);