Lines Matching +full:32 +full:- +full:bits
1 //===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
23 bits<5> vry;
24 bits<5> vrx;
25 bits<5> vrz;
27 let Inst{25-21} = vry;
28 let Inst{20-16} = vrx;
29 let Inst{15-11} = datatype;
30 let Inst{10-5} = sop;
31 let Inst{4-0} = vrz;
34 multiclass F2_XYZ_T<bits<6> sop, string op, PatFrag opnode> {
35 def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
45 multiclass F2_XYZZ_T<bits<6> sop, string op, PatFrag opnode> {
46 def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
56 class F2_XZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op, SDNode opnode>
61 class F2_XZ_SET<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
66 class F2_XZ_P<bits<5> datatype, bits<6> sop, string op, list<dag> pattern = [],
71 multiclass F2_XZ_RM<bits<5> datatype, bits<4> sop, string op, dag outs, dag ins> {
78 multiclass F2_XZ_T<bits<6> sop, string op, SDNode opnode> {
79 def _S : F2_XZ<0b00000, FPR32Op, sop, op#".32", opnode>;
84 multiclass F2_XZ_SET_T<bits<6> sop, string op, string suffix = ""> {
85 def _S : F2_XZ_SET<0b00000, FPR32Op, sop, op#".32"#suffix>;
92 class F2_CXY<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
97 multiclass F2_CXY_T<bits<6> sop, string op> {
98 def _S : F2_CXY<0b00000, FPR32Op, sop, op#".32">;
105 class F2_CX<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
110 multiclass F2_CX_T<bits<6> sop, string op> {
111 def _S : F2_CX<0b00000, FPR32Op, sop, op#".32">;
117 class F2_LDST<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
120 bits<10> imm8;
121 bits<5> rx;
122 bits<5> vrz;
125 let Inst{24-21} = imm8{7-4};
126 let Inst{20-16} = rx;
127 let Inst{15-11} = 0b00100;
129 let Inst{9-8} = datatype;
130 let Inst{7-4} = imm8{3-0};
131 let Inst{3-0} = vrz{3-0};
134 class F2_LDST_S<bits<1> sop, string op, dag outs, dag ins>
135 : F2_LDST<0b00, sop, op#".32", outs, ins>;
136 class F2_LDST_D<bits<1> sop, string op, dag outs, dag ins>
139 class F2_LDSTM<bits<2> datatype, bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
142 bits<10> regs;
143 bits<5> rx;
145 let Inst{25-21} = regs{4-0};
146 let Inst{20-16} = rx;
147 let Inst{15-11} = 0b00110;
149 let Inst{9-8} = datatype;
150 let Inst{7-5} = sop2;
151 let Inst{4-0} = regs{9-5};
154 class F2_LDSTM_S<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
155 : F2_LDSTM<0b00, sop, sop2, op#".32", outs, ins>;
156 class F2_LDSTM_D<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
160 class F2_LDSTR<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
163 bits<5> rx;
164 bits<5> ry;
165 bits<5> rz;
166 bits<2> imm;
168 let Inst{25-21} = ry;
169 let Inst{20-16} = rx;
170 let Inst{15-11} = 0b00101;
172 let Inst{9-8} = datatype;
174 let Inst{6-5} = imm;
175 let Inst{4-0} = rz;
178 class F2_LDSTR_S<bits<1> sop, string op, dag outs, dag ins>
179 : F2_LDSTR<0b00, sop, op#".32", outs, ins>;
180 class F2_LDSTR_D<bits<1> sop, string op, dag outs, dag ins>
183 class F2_CXYZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
187 multiclass F2_CXYZ_T<bits<6> sop, string op> {
188 def _S : F2_CXYZ<0b00000, FPR32Op, sop, op#".32">;
193 class F2_LRW<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
196 bits<10> imm8;
197 bits<5> rx;
198 bits<5> vrz;
201 let Inst{24-21} = imm8{7-4};
202 let Inst{20-16} = 0;
203 let Inst{15-11} = 0b00111;
205 let Inst{9-8} = datatype;
206 let Inst{7-4} = imm8{3-0};
207 let Inst{3-0} = vrz{3-0};