Lines Matching +full:16 +full:- +full:bits
1 //===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
16 def AddrMode32WD : AddrMode<3>; // ld32.w, st32.w, ld32.d, st32.d, +16kb
27 field bits<32> SoftFail = 0;
33 let TSFlags{4 - 0} = AM.Value;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
45 field bits<32> Inst;
46 let Inst{31 - 26} = opcode;
51 field bits<16> Inst;
54 // CSKY 32-bit instruction
57 class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
60 bits<26> offset;
61 let Inst{25 - 0} = offset;
68 class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
70 bits<5> rz;
71 bits<18> offset;
72 let Inst{25 - 21} = rz;
73 let Inst{20 - 18} = sop;
74 let Inst{17 - 0} = offset;
77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
83 bits<5> rz;
84 bits<5> rx;
85 bits<16> imm16;
86 let Inst{25 - 21} = rz;
87 let Inst{20 - 16} = rx;
88 let Inst{15 - 0} = imm16;
91 // Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
93 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
97 bits<5> rz;
98 bits<16> imm16;
99 let Inst{25 - 21} = sop;
100 let Inst{20 - 16} = rz;
101 let Inst{15 - 0} = imm16;
107 // Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
109 class I_16_Z_L<bits<5> sop, string op, dag ins, list<dag> pattern>
112 bits<5> rz;
113 bits<16> imm16;
114 let Inst{25 - 21} = sop;
115 let Inst{20 - 16} = rz;
116 let Inst{15 - 0} = imm16;
119 // Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
121 class I_16_L<bits<5> sop, dag outs, dag ins, string asm, list<dag> pattern>
123 bits<16> imm16;
124 let Inst{25 - 21} = sop;
125 let Inst{20 - 16} = 0;
126 let Inst{15 - 0} = imm16;
129 // Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
131 class I_16_JX<bits<5> sop, string op, list<dag> pattern>
134 bits<5> rx;
135 bits<16> imm16;
136 let Inst{25 - 21} = sop;
137 let Inst{20 - 16} = rx;
138 let Inst{15 - 0} = 0;
143 class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
147 bits<5> rx;
148 bits<2> imm2;
149 let Inst{25 - 21} = sop;
150 let Inst{20 - 16} = rx;
151 let Inst{15 - 2} = 0;
152 let Inst{1 - 0} = imm2;
155 // Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
157 class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
159 let Inst{25 - 21} = sop;
160 let Inst{20 - 16} = pcode;
161 let Inst{15 - 0} = 0;
168 // Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
170 class I_16_X<bits<5> sop, string op, Operand operand>
173 bits<16> imm16;
174 bits<5> rx;
175 let Inst{25 - 21} = sop;
176 let Inst{20 - 16} = rx;
177 let Inst{15 - 0} = imm16;
181 // Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
183 class I_16_X_L<bits<5> sop, string op, Operand operand>
186 bits<5> rx;
187 bits<16> imm16;
188 let Inst{25 - 21} = sop;
189 let Inst{20 - 16} = rx;
190 let Inst{15 - 0} = imm16;
197 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
201 bits<5> rz;
202 bits<5> rx;
203 bits<12> imm12;
204 let Inst{25 - 21} = rz;
205 let Inst{20 - 16} = rx;
206 let Inst{15 - 12} = sop;
207 let Inst{11 - 0} = imm12;
210 class I_LDST<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
214 bits<5> rx;
215 bits<5> rz;
216 bits<12> imm12;
217 let Inst{25 - 21} = rz;
218 let Inst{20 - 16} = rx;
219 let Inst{15 - 12} = sop;
220 let Inst{11 - 0} = imm12;
223 class I_PLDR<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
227 bits<5> rx;
228 bits<12> imm12;
229 let Inst{25 - 21} = 0;
230 let Inst{20 - 16} = rx;
231 let Inst{15 - 12} = sop;
232 let Inst{11 - 0} = imm12;
238 class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
244 class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
251 class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
253 bits<12> regs;
254 let Inst{25 - 21} = sop;
255 let Inst{20 - 16} = pcode;
256 let Inst{15 - 12} = 0;
257 let Inst{11 - 0} = regs;
264 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
269 bits<5> rz;
270 bits<5> rx;
271 bits<5> imm5;
272 let Inst{25 - 21} = rz;
273 let Inst{20 - 16} = rx;
274 let Inst{15 - 10} = sop;
275 let Inst{9 - 5} = pcode;
276 let Inst{4 - 0} = imm5;
283 class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag outs, dag ins,
287 bits<5> imm5;
288 bits<5> rx;
289 bits<5> rz;
290 let Inst{25 - 21} = imm5;
291 let Inst{20 - 16} = rx;
292 let Inst{15 - 10} = sop;
293 let Inst{9 - 5} = pcode;
294 let Inst{4 - 0} = rz;
298 class I_5_XZ_CR<bits<6> sop, bits<5> pcode, string opStr, dag outs, dag ins,
301 bits<5> sel;
302 bits<5> rx;
303 bits<5> cr;
304 let Inst{25 - 21} = sel;
305 let Inst{20 - 16} = rx;
306 let Inst{15 - 10} = sop;
307 let Inst{9 - 5} = pcode;
308 let Inst{4 - 0} = cr;
312 class I_5_XZ_SYNC<bits<6> sop, bits<5> pcode, string opStr, bits<1> S, bits<1> I>
314 let Inst{25 - 21} = 0;
315 let Inst{20 - 16} = 0;
316 let Inst{15 - 10} = sop;
317 let Inst{9 - 5} = pcode;
318 let Inst{4 - 0} = 0;
325 class I_5_XZ_PRIVI<bits<6> sop, bits<5> pcode, string opStr>
327 let Inst{25 - 21} = 0;
328 let Inst{20 - 16} = 0;
329 let Inst{15 - 10} = sop;
330 let Inst{9 - 5} = pcode;
331 let Inst{4 - 0} = 0;
334 class I_CP<bits<4> sop, dag outs, dag ins, string opStr>
336 bits<5> cpid;
337 bits<12> usdef;
338 let Inst{25 - 21} = cpid;
339 let Inst{20 - 16} = 0;
340 let Inst{15 - 12} = sop;
341 let Inst{11 - 0} = usdef;
346 bits<5> cpid;
347 bits<20> usdef;
348 let Inst{25 - 21} = cpid;
349 let Inst{20 - 16} = usdef{19-15};
351 let Inst{14 - 0} = usdef{14-0};
354 class I_CP_Z<bits<4> sop, dag outs, dag ins, string opStr>
356 bits<5> cpid;
357 bits<12> usdef;
358 bits<5> rz;
360 let Inst{25 - 21} = cpid;
361 let Inst{20 - 16} = rz;
362 let Inst{15 - 12} = sop;
363 let Inst{11 - 0} = usdef;
366 class I_5_CACHE<bits<6> sop, bits<5> pcode, string opStr>
368 let Inst{25 - 21} = pcode;
369 let Inst{20 - 16} = 0;
370 let Inst{15 - 10} = sop;
371 let Inst{9 - 5} = 0b00001;
372 let Inst{4 - 0} = 0;
375 class I_5_X_CACHE<bits<6> sop, bits<5> pcode, string opStr>
377 bits<5> rx;
379 let Inst{25 - 21} = pcode;
380 let Inst{20 - 16} = rx;
381 let Inst{15 - 10} = sop;
382 let Inst{9 - 5} = 0b00001;
383 let Inst{4 - 0} = 0;
388 class I_5_YX<bits<6> opcode, bits<6> sop, dag outs, dag ins, string opStr, list<dag> pattern>
390 bits<10> regs;
391 bits<5> rx;
393 let Inst{25 - 21} = regs{9 - 5}; // ry
394 let Inst{20 - 16} = rx;
395 let Inst{15 - 10} = sop;
396 let Inst{9 - 5} = 0b00001;
397 let Inst{4 - 0} = regs{4 - 0}; // imm5
402 class I_5_XZ_U<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
405 bits<5> rx;
406 bits<5> rz;
407 bits<5> msb;
408 bits<5> lsb;
409 let Inst{25 - 21} = lsb; // lsb
410 let Inst{20 - 16} = rx;
411 let Inst{15 - 10} = sop;
412 let Inst{9 - 5} = msb; // msb
413 let Inst{4 - 0} = rz;
416 class I_5_XZ_INS<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
419 bits<5> rx;
420 bits<5> rz;
421 bits<5> msb;
422 bits<5> lsb;
423 let Inst{25 - 21} = rz;
424 let Inst{20 - 16} = rx;
425 let Inst{15 - 10} = sop;
426 let Inst{9 - 5} = msb;
427 let Inst{4 - 0} = lsb;
432 class I_5_XZ_U2<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
435 bits<5> rx;
436 bits<5> rz;
437 let Inst{25 - 21} = lsb; // lsb
438 let Inst{20 - 16} = rx;
439 let Inst{15 - 10} = sop;
440 let Inst{9 - 5} = msb; // msb
441 let Inst{4 - 0} = rz;
446 class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
449 bits<10> size_lsb;
450 bits<5> rz;
451 bits<5> rx;
452 let Inst{25 - 21} = rz;
453 let Inst{20 - 16} = rx;
454 let Inst{15 - 10} = sop;
455 let Inst{9 - 5} = size_lsb{9 - 5}; // size
456 let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
460 class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op,
465 class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
471 class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
476 bits<5> imm5;
477 bits<5> rx;
478 let Inst{25 - 21} = imm5;
479 let Inst{20 - 16} = rx;
480 let Inst{15 - 10} = sop;
481 let Inst{9 - 5} = pcode;
482 let Inst{4 - 0} = 0;
488 class I_5_Z<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
492 bits<5> imm5;
493 bits<5> rz;
494 let Inst{25 - 21} = imm5;
495 let Inst{20 - 16} = 0;
496 let Inst{15 - 10} = sop;
497 let Inst{9 - 5} = pcode;
498 let Inst{4 - 0} = rz;
501 class I_5_IMM5<bits<6> opcode, bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
505 bits<5> imm5;
506 let Inst{25 - 21} = imm5;
507 let Inst{20 - 16} = 0;
508 let Inst{15 - 10} = sop;
509 let Inst{9 - 5} = pcode;
510 let Inst{4 - 0} = 0;
517 class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
521 bits<5> ry;
522 bits<5> rx;
523 bits<5> rz;
524 let Inst{25 - 21} = ry;
525 let Inst{20 - 16} = rx;
526 let Inst{15 - 10} = sop;
527 let Inst{9 - 5} = pcode;
528 let Inst{4 - 0} = rz;
537 class R_YXZ_SP_F1<bits<6> sop, bits<5> pcode, PatFrag opnode, string op,
546 class R_YXZ_LDST<bits<6> opcode, bits<6> sop, dag outs,
550 bits<5> rx;
551 bits<5> ry;
552 bits<5> rz;
553 bits<5> imm;
554 let Inst{25 - 21} = ry; // ry;
555 let Inst{20 - 16} = rx; // rx;
556 let Inst{15 - 10} = sop;
557 let Inst{9 - 5} = imm; // pcode;
558 let Inst{4 - 0} = rz;
561 class I_LDR<bits<6> sop, string op> : R_YXZ_LDST<0x34, sop,
564 class I_STR<bits<6> sop, string op> : R_YXZ_LDST<0x35, sop,
569 class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
573 bits<5> rx;
574 bits<5> rz;
575 let Inst{25 - 21} = rx;
576 let Inst{20 - 16} = rx;
577 let Inst{15 - 10} = sop;
578 let Inst{9 - 5} = pcode;
579 let Inst{4 - 0} = rz;
584 class R_YX<bits<6> sop, bits<5> pcode, string op>
588 bits<5> ry;
589 bits<5> rx;
590 let Inst{25 - 21} = ry;
591 let Inst{20 - 16} = rx;
592 let Inst{15 - 10} = sop;
593 let Inst{9 - 5} = pcode;
594 let Inst{4 - 0} = 0;
602 class R_XZ<bits<6> sop, bits<5> pcode, string op>
605 bits<5> rx;
606 bits<5> rz;
607 let Inst{25 - 21} = 0;
608 let Inst{20 - 16} = rx;
609 let Inst{15 - 10} = sop;
610 let Inst{9 - 5} = pcode;
611 let Inst{4 - 0} = rz;
616 class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
620 bits<5> rz;
621 bits<5> rx;
622 let Inst{25 - 21} = rz;
623 let Inst{20 - 16} = rx;
624 let Inst{15 - 10} = sop;
625 let Inst{9 - 5} = pcode;
626 let Inst{4 - 0} = 0;
633 class R_X<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op, list<dag> pattern>
635 bits<5> rx;
636 let Inst{25 - 21} = 0;
637 let Inst{20 - 16} = rx;
638 let Inst{15 - 10} = sop;
639 let Inst{9 - 5} = pcode;
640 let Inst{4 - 0} = 0;
645 class R_Z_1<bits<6> sop, bits<5> pcode, string op>
648 bits<5> rz;
649 let Inst{25 - 21} = 0;
650 let Inst{20 - 16} = 0;
651 let Inst{15 - 10} = sop;
652 let Inst{9 - 5} = pcode;
653 let Inst{4 - 0} = rz;
658 class R_Z_2<bits<6> sop, bits<5> pcode, string op>
661 bits<5> rz;
662 let Inst{25 - 21} = rz;
663 let Inst{20 - 16} = 0;
664 let Inst{15 - 10} = sop;
665 let Inst{9 - 5} = pcode;
666 let Inst{4 - 0} = 0;
670 class BAR<bits<5> sop, string op, bits<1> signed>
673 let Inst{24 - 16} = 0;
674 let Inst{15 - 5} = 0x421;
675 let Inst{4 - 0} = sop;