Lines Matching +full:ext +full:- +full:regs
1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
78 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
198 // extending 8-bit to 16-bit. This may require infrastructure
199 // improvements in how we treat 16-bit "registers" to be feasible.
270 "Expected power-of-2 shift amount");
273 if (!isa<ConstantSDNode>(N->getOperand(1))) {
274 // 32-bit shifts are converted to a loop in IR.
285 uint64_t ShiftAmount = N->getConstantOperandVal(1);
288 // generic codegen parts to lower 32-bit numbers.
289 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
290 // shift of a part of the 32-bit value?
306 llvm_unreachable("Invalid 32-bit shift opcode!");
322 // Expand non-constant shifts to loops.
323 if (!isa<ConstantSDNode>(N->getOperand(1))) {
328 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
329 N->getOperand(1));
331 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
332 N->getOperand(1));
334 SDValue Amt = N->getOperand(1);
337 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
338 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
341 SDValue Amt = N->getOperand(1);
344 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
345 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
348 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
349 N->getOperand(1));
353 uint64_t ShiftAmount = N->getConstantOperandVal(1);
354 SDValue Victim = N->getOperand(0);
385 ShiftAmount -= 4;
392 ShiftAmount -= 4;
439 ShiftAmount -= 4;
468 ShiftAmount -= 4;
473 ShiftAmount -= 4;
483 ShiftAmount -= 8;
490 ShiftAmount -= 8;
497 ShiftAmount -= 8;
509 ShiftAmount -= 12;
516 ShiftAmount -= 12;
523 ShiftAmount -= 8;
532 while (ShiftAmount--) {
540 unsigned Opcode = Op->getOpcode();
544 EVT VT = Op->getValueType(0);
566 for (SDValue const &Value : Op->op_values()) {
596 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
597 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
608 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
615 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
635 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
647 uint64_t Imm = RHS->getAsZExtVal();
648 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
665 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
667 uint64_t Imm = LHS->getAsZExtVal();
683 // Generate ordinary 16-bit comparison.
710 switch (C->getSExtValue()) {
711 case -1: {
712 // When doing lhs > -1 use a tst instruction on the top part of lhs
729 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
743 switch (C->getSExtValue()) {
773 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
870 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
888 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
903 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
920 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
926 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
935 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg ||
936 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) {
946 // - The flags of the implicit zero register operand.
947 // - The implicit zero register operand itself.
952 for (unsigned I = 0; I < N->getNumOperands(); I++) {
953 SDValue Operand = N->getOperand(I);
971 SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
1017 switch (N->getOpcode()) {
1019 // Convert add (x, imm) into sub (x, -imm).
1020 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1022 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
1023 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
1031 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1059 Offs = -Offs;
1070 /// can be legally represented as pre-indexed load / store address.
1080 VT = LD->getMemoryVT();
1081 Op = LD->getBasePtr().getNode();
1082 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1088 VT = ST->getMemoryVT();
1089 Op = ST->getBasePtr().getNode();
1101 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1105 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1106 int RHSC = RHS->getSExtValue();
1107 if (Op->getOpcode() == ISD::SUB)
1108 RHSC = -RHSC;
1110 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1114 Base = Op->getOperand(0);
1126 /// combined with a load / store to form a post-indexed load / store.
1136 VT = LD->getMemoryVT();
1137 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1140 VT = ST->getMemoryVT();
1158 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1162 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1163 int RHSC = RHS->getSExtValue();
1164 if (Op->getOpcode() == ISD::SUB)
1165 RHSC = -RHSC;
1171 // due to bug https://github.com/llvm/llvm-project/issues/59914.
1176 Base = Op->getOperand(0);
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1215 "8-bit and 16-bit register arrays must be of equal length");
1217 "8-bit and 16-bit register arrays must be of equal length");
1242 // -1 means R26 (R26 is never actually used in CC).
1243 int RegLastIdx = -1;
1277 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1278 TD->getABITypeAlign(evt));
1295 RegIdx -= VT.getStoreSize();
1340 // GCC-ABI says that the size is rounded up to the next even number,
1349 int RegIdx = TotalBytes - 1;
1363 RegIdx -= VT.getStoreSize();
1410 // to 16 bits. Insert an assert[sz]ext to capture this, then
1457 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1463 //===----------------------------------------------------------------------===//
1465 //===----------------------------------------------------------------------===//
1495 const GlobalValue *GV = G->getGlobal();
1502 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1590 // Build a sequence of copy-to-reg nodes chained together with token chain and
1615 // Add a register mask operand representing the call-preserved registers.
1618 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1674 //===----------------------------------------------------------------------===//
1676 //===----------------------------------------------------------------------===//
1697 // CCValAssign - represent the assignment of the return value to locations.
1700 // CCState - Info about the registers and stack slot.
1735 if (!AFI->isInterruptOrSignalHandler()) {
1744 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_GLUE : AVRISD::RET_GLUE;
1755 //===----------------------------------------------------------------------===//
1757 //===----------------------------------------------------------------------===//
1765 MachineFunction *F = BB->getParent();
1766 MachineRegisterInfo &RI = F->getRegInfo();
1816 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1819 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1821 if (I != F->end())
1825 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1826 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1827 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1829 F->insert(I, LoopBB);
1830 F->insert(I, CheckBB);
1831 F->insert(I, RemBB);
1833 // Update machine-CFG edges by transferring all successors of the current
1835 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1836 BB->end());
1837 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1840 BB->addSuccessor(CheckBB);
1841 LoopBB->addSuccessor(CheckBB);
1842 CheckBB->addSuccessor(LoopBB);
1843 CheckBB->addSuccessor(RemBB);
1867 // ShiftAmt2 = ShiftAmt - 1;
1893 // registers in the Regs array.
1902 // https://aykevl.nl/2021/02/avr-bitshift
1904 MutableArrayRef<std::pair<Register, int>> Regs,
1906 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1907 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1908 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1929 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1931 Regs.slice(ShiftRegsOffset, ShiftRegsSize);
1942 // Shift one more to the right if this is a modulo-6 shift.
1951 for (size_t I = 0; I < Regs.size(); I++) {
1954 Regs[I] = ShiftRegs[ShiftRegsIdx];
1956 Regs[I] = std::pair(LowByte, 0);
1958 Regs[I] = std::pair(ZeroReg, 0);
1969 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1971 Regs.slice(0, ShiftRegsSize);
1983 // Sign-extend bit that was shifted out last.
1988 // The highest bit of the original value is the same as the zero-extend
2011 for (int I = Regs.size() - 1; I >= 0; I--) {
2012 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
2014 Regs[I] = ShiftRegs[ShiftRegsIdx];
2015 } else if (ShiftRegsIdx == -1) {
2016 Regs[I] = std::pair(HighByte, 0);
2018 Regs[I] = std::pair(ExtByte, 0);
2029 for (size_t I = 0; I < Regs.size() - 1; I++) {
2030 Regs[I] = Regs[I + 1];
2034 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
2037 Regs = Regs.drop_back(1);
2039 ShiftAmt -= 8;
2050 .addReg(Regs[0].first, 0, Regs[0].second)
2051 .addReg(Regs[0].first, 0, Regs[0].second);
2058 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2060 for (size_t I = Regs.size() - 1; I != 0; I--) {
2061 Regs[I] = Regs[I - 1];
2065 Regs[0] = std::pair(ShrExtendReg, 0);
2068 Regs = Regs.drop_front(1);
2081 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2087 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2088 // (24-bit) shift it adds:
2095 for (size_t I = 0; I < Regs.size(); I++) {
2096 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2099 .addReg(Regs[Idx].first, 0, Regs[Idx].second);
2116 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2117 Regs[PrevIdx] = std::pair(R, 0);
2120 Regs[Idx] = std::pair(AndReg, 0);
2122 ShiftAmt -= 4;
2129 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2131 Register In = Regs[I].first;
2132 Register InSubreg = Regs[I].second;
2133 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2142 Regs[I] = std::pair(Out, 0);
2144 ShiftAmt--;
2148 for (size_t I = 0; I < Regs.size(); I++) {
2150 Register In = Regs[I].first;
2151 Register InSubreg = Regs[I].second;
2158 Regs[I] = std::pair(Out, 0);
2160 ShiftAmt--;
2168 // Do a wide (32-bit) shift.
2199 // Do the shift. The registers are modified in-place.
2202 // Combine the 8-bit registers into 16-bit register pairs.
2207 // - lsl prefers starting from the most significant byte (2nd case).
2208 // - lshr prefers starting from the least significant byte (1st case).
2209 // - for ashr it depends on the number of shifted bytes.
2212 // already equal to or faster than avr-gcc in all cases except ashr 8).
2246 if (I->getOpcode() == AVR::COPY) {
2247 Register SrcReg = I->getOperand(1).getReg();
2289 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2294 // Example instruction sequence, for an atomic 8-bit add:
2342 const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
2393 ->getParent()
2394 ->getSubtarget()
2399 // control-flow pattern. The incoming instruction knows the
2404 MachineFunction *MF = MBB->getParent();
2405 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2406 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2415 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2416 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2419 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2421 if (I != MF->end())
2423 MF->insert(I, trueMBB);
2424 MF->insert(I, falseMBB);
2428 trueMBB->setCallFrameSize(CallFrameSize);
2429 falseMBB->setCallFrameSize(CallFrameSize);
2434 trueMBB->splice(trueMBB->begin(), MBB,
2435 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2436 trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
2441 MBB->addSuccessor(falseMBB);
2442 MBB->addSuccessor(trueMBB);
2446 falseMBB->addSuccessor(trueMBB);
2449 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
2460 //===----------------------------------------------------------------------===//
2462 //===----------------------------------------------------------------------===//
2467 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2491 case 'I': // 6-bit positive integer constant
2492 case 'J': // 6-bit negative integer constant
2495 case 'M': // 8-bit integer constant
2496 case 'N': // Integer constant (Range: -1)
2499 case 'R': // Integer constant (Range: -6 to 5)x
2557 if (C->isZero()) {
2564 if (isUInt<6>(C->getZExtValue())) {
2571 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2578 if (C->getZExtValue() == 2) {
2585 if (C->getZExtValue() == 0) {
2592 if (isUInt<8>(C->getZExtValue())) {
2599 if (C->getSExtValue() == -1) {
2606 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2607 (C->getZExtValue() == 24)) {
2614 if (C->getZExtValue() == 1) {
2621 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2739 int64_t CVal64 = C->getSExtValue();
2740 uint64_t CUVal64 = C->getZExtValue();
2747 case 'J': // -63..0
2748 if (CVal64 < -63 || CVal64 > 0)
2766 // e.g. 254 would be printed as -2,
2773 case 'N': // -1
2774 if (CVal64 != -1)
2788 case 'R': // -6..5
2789 if (CVal64 < -6 || CVal64 > 5)
2799 if (!FC || !FC->isZero())