Lines Matching defs:DestReg
135 Register DestReg = MI.getOperand(0).getReg();
137 if (!DestReg.isVirtual())
141 get(ARM::t2CSEL), DestReg)
153 const DebugLoc &DL, MCRegister DestReg,
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
157 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
211 Register DestReg, int FI,
224 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
236 if (DestReg.isVirtual()) {
238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
246 if (DestReg.isPhysical())
247 MIB.addReg(DestReg, RegState::ImplicitDefine);
251 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI,
311 const DebugLoc &dl, Register DestReg,
316 if (NumBytes == 0 && DestReg != BaseReg) {
317 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
328 if (DestReg != ARM::SP && DestReg != BaseReg &&
334 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
340 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
341 .addReg(DestReg)
349 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
351 .addReg(DestReg, RegState::Kill)
356 // Here we know that DestReg is not SP but we do not
361 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
363 .addReg(DestReg, RegState::Kill)
375 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
377 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
385 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
389 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
392 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
401 bool ToSP = DestReg == ARM::SP;
427 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
435 BaseReg = DestReg;