Lines Matching +full:0 +full:xc000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
239 case ARM_AM::da: return 0; in getLdStmModeOpValue()
251 case ARM_AM::lsl: return 0; in getShiftOp()
311 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or in getCCOutOpValue()
326 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getModImmOpValue()
327 return 0; in getModImmOpValue()
345 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getT2SOImmOpValue()
346 return 0; in getT2SOImmOpValue()
350 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); in getT2SOImmOpValue()
477 unsigned Bit24 = EncodedValue & 0x01000000; in NEONThumb2DataIPostEncoder()
479 EncodedValue &= 0xEFFFFFFF; in NEONThumb2DataIPostEncoder()
481 EncodedValue |= 0x0F000000; in NEONThumb2DataIPostEncoder()
494 EncodedValue &= 0xF0FFFFFF; in NEONThumb2LoadStorePostEncoder()
495 EncodedValue |= 0x09000000; in NEONThumb2LoadStorePostEncoder()
508 EncodedValue &= 0x00FFFFFF; in NEONThumb2DupPostEncoder()
509 EncodedValue |= 0xEE000000; in NEONThumb2DupPostEncoder()
521 EncodedValue |= 0xC000000; // Set bits 27-26 in NEONThumb2V8PostEncoder()
533 EncodedValue &= 0x0FFFFFFF; in VFPThumb2PostEncoder()
534 EncodedValue |= 0xE0000000; in VFPThumb2PostEncoder()
592 // Special value for #-0 in EncodeAddrModeOpValues()
594 SImm = 0; in EncodeAddrModeOpValues()
599 if (SImm < 0) { in EncodeAddrModeOpValues()
621 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getBranchTargetOpValue()
624 return 0; in getBranchTargetOpValue()
631 uint32_t S = (offset & 0x800000) >> 23; in encodeThumbBLOffset()
632 uint32_t J1 = (offset & 0x400000) >> 22; in encodeThumbBLOffset()
633 uint32_t J2 = (offset & 0x200000) >> 21; in encodeThumbBLOffset()
634 J1 = (~J1 & 0x1); in encodeThumbBLOffset()
635 J2 = (~J2 & 0x1); in encodeThumbBLOffset()
639 offset &= ~0x600000; in encodeThumbBLOffset()
710 for (int i = 0; i < NumOp-1; ++i) { in HasConditionalBranch()
714 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()
786 unsigned Val = 0; in getThumbBranchTargetOpValue()
794 bool I = (Val & 0x800000); in getThumbBranchTargetOpValue()
795 bool J1 = (Val & 0x400000); in getThumbBranchTargetOpValue()
796 bool J2 = (Val & 0x200000); in getThumbBranchTargetOpValue()
798 Val &= ~0x400000; in getThumbBranchTargetOpValue()
800 Val |= 0x400000; in getThumbBranchTargetOpValue()
803 Val &= ~0x200000; in getThumbBranchTargetOpValue()
805 Val |= 0x200000; in getThumbBranchTargetOpValue()
821 uint32_t Val = 0x2000; in getAdrLabelOpValue()
825 Val = 0x1000; in getAdrLabelOpValue()
826 SoImmVal = 0; in getAdrLabelOpValue()
827 } else if (offset < 0) { in getAdrLabelOpValue()
828 Val = 0x1000; in getAdrLabelOpValue()
832 Val = 0x2000; in getAdrLabelOpValue()
839 Val = 0x1000; in getAdrLabelOpValue()
863 Val = 0x1000; in getT2AdrLabelOpValue()
864 else if (Val < 0) { in getT2AdrLabelOpValue()
866 Val |= 0x1000; in getT2AdrLabelOpValue()
886 assert(OpIdx > 0 && "IT mask appears first!"); in getITMaskOpValue()
891 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); in getITMaskOpValue()
919 // {2-0} = Rn in getThumbAddrModeRegRegOpValue()
933 // {4-0} = szimm5 in getMVEShiftImmOpValue()
968 // {12} = (U)nsigned (add == '1', sub == '0') in getAddrModeImm12OpValue()
969 // {11-0} = imm12 in getAddrModeImm12OpValue()
970 unsigned Reg = 0, Imm12 = 0; in getAddrModeImm12OpValue()
984 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc())); in getAddrModeImm12OpValue()
994 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc())); in getAddrModeImm12OpValue()
1001 Offset = 0; in getAddrModeImm12OpValue()
1003 } else if (Offset < 0) { in getAddrModeImm12OpValue()
1009 uint32_t Binary = Imm12 & 0xfff; in getAddrModeImm12OpValue()
1027 // for #-0. in getT2ScaledImmOpValue()
1029 // {Bits} = (U)nsigned (add == '1', sub == '0') in getT2ScaledImmOpValue()
1030 // {(Bits-1)-0} = immediate in getT2ScaledImmOpValue()
1032 bool isAdd = Imm >= 0; in getT2ScaledImmOpValue()
1035 if (Imm < 0) in getT2ScaledImmOpValue()
1054 // {2-0} Qm in getMveAddrModeRQOpValue()
1074 // {7-0} Imm in getMveAddrModeQOpValue()
1081 bool isAdd = Imm >= 0; in getMveAddrModeQOpValue()
1088 Imm &= 0x7f; in getMveAddrModeQOpValue()
1091 Imm |= 0x80; in getMveAddrModeQOpValue()
1105 // {8} = (U)nsigned (add == '1', sub == '0') in getT2AddrModeImm8s4OpValue()
1106 // {7-0} = imm8 in getT2AddrModeImm8s4OpValue()
1113 Imm8 = 0; in getT2AddrModeImm8s4OpValue()
1119 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getT2AddrModeImm8s4OpValue()
1130 // for #-0. in getT2AddrModeImm8s4OpValue()
1131 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!"); in getT2AddrModeImm8s4OpValue()
1132 uint32_t Binary = (Imm8 >> 2) & 0xff; in getT2AddrModeImm8s4OpValue()
1147 // {7} = (A)dd (add == '1', sub == '0') in getT2AddrModeImm7s4OpValue()
1148 // {6-0} = imm7 in getT2AddrModeImm7s4OpValue()
1158 // for #-0. in getT2AddrModeImm7s4OpValue()
1159 uint32_t Binary = (Imm7 >> 2) & 0xff; in getT2AddrModeImm7s4OpValue()
1174 // {7-0} = imm8 in getT2AddrModeImm0_1020s4OpValue()
1186 // {11-0} = imm{11-0} in getHiLoImmOpValue()
1207 return (int32_t(Value) & 0xffff0000) >> 16; in getHiLoImmOpValue()
1209 return (int32_t(Value) & 0x0000ffff); in getHiLoImmOpValue()
1212 return (int32_t(Value) & 0xff000000) >> 24; in getHiLoImmOpValue()
1214 return (int32_t(Value) & 0x00ff0000) >> 16; in getHiLoImmOpValue()
1216 return (int32_t(Value) & 0x0000ff00) >> 8; in getHiLoImmOpValue()
1218 return (int32_t(Value) & 0x000000ff); in getHiLoImmOpValue()
1256 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); in getHiLoImmOpValue()
1257 return 0; in getHiLoImmOpValue()
1283 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift in getLdStSORegOpValue()
1285 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); in getLdStSORegOpValue()
1289 // {11-0} = shifter in getLdStSORegOpValue()
1290 // {3-0} = Rm in getLdStSORegOpValue()
1291 // {4} = 0 in getLdStSORegOpValue()
1307 // {13} 1 == imm12, 0 == Rm in getAddrMode2OffsetOpValue()
1309 // {11-0} imm12/Rm in getAddrMode2OffsetOpValue()
1314 bool isReg = MO.getReg() != 0; in getAddrMode2OffsetOpValue()
1321 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] in getAddrMode2OffsetOpValue()
1331 // {3-0} Rm in getPostIdxRegOpValue()
1334 bool isAdd = MO1.getImm() != 0; in getPostIdxRegOpValue()
1342 // {9} 1 == imm8, 0 == Rm in getAddrMode3OffsetOpValue()
1345 // {3-0} imm3_0/Rm in getAddrMode3OffsetOpValue()
1350 bool isImm = MO.getReg() == 0; in getAddrMode3OffsetOpValue()
1362 // {13} 1 == imm8, 0 == Rm in getAddrMode3OpValue()
1366 // {3-0} imm3_0/Rm in getAddrMode3OpValue()
1378 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getAddrMode3OpValue()
1386 bool isImm = MO1.getReg() == 0; in getAddrMode3OpValue()
1400 // {7-0} = imm8 in getAddrModeThumbSPOpValue()
1407 return MO1.getImm() & 0xff; in getAddrModeThumbSPOpValue()
1417 // {2-0} = Rn in getAddrModeISOpValue()
1422 return ((Imm5 & 0x1f) << 3) | Rn; in getAddrModeISOpValue()
1442 // {8} = (U)nsigned (add == '1', sub == '0') in getAddrMode5OpValue()
1443 // {7-0} = imm8 in getAddrMode5OpValue()
1450 Imm8 = 0; in getAddrMode5OpValue()
1460 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getAddrMode5OpValue()
1482 // {8} = (U)nsigned (add == '1', sub == '0') in getAddrMode5FP16OpValue()
1483 // {7-0} = imm8 in getAddrMode5FP16OpValue()
1490 Imm8 = 0; in getAddrMode5FP16OpValue()
1500 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); in getAddrMode5FP16OpValue()
1524 // {3-0} = Rm. in getSORegRegOpValue()
1528 // {7} = 0 in getSORegRegOpValue()
1539 unsigned SBits = 0; in getSORegRegOpValue()
1549 case ARM_AM::lsl: SBits = 0x1; break; in getSORegRegOpValue()
1550 case ARM_AM::lsr: SBits = 0x3; break; in getSORegRegOpValue()
1551 case ARM_AM::asr: SBits = 0x5; break; in getSORegRegOpValue()
1552 case ARM_AM::ror: SBits = 0x7; break; in getSORegRegOpValue()
1560 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); in getSORegRegOpValue()
1571 // {3-0} = Rm. in getSORegImmOpValue()
1572 // {4} = 0 in getSORegImmOpValue()
1584 unsigned SBits = 0; in getSORegImmOpValue()
1594 case ARM_AM::lsl: SBits = 0x0; break; in getSORegImmOpValue()
1595 case ARM_AM::lsr: SBits = 0x2; break; in getSORegImmOpValue()
1596 case ARM_AM::asr: SBits = 0x4; break; in getSORegImmOpValue()
1597 case ARM_AM::ror: SBits = 0x6; break; in getSORegImmOpValue()
1599 Binary |= 0x60; in getSORegImmOpValue()
1606 assert(Offset < 32 && "Offset must be in range 0-31!"); in getSORegImmOpValue()
1646 tmp = 0; in getT2AddrModeImmOpValue()
1647 } else if (tmp < 0) { in getT2AddrModeImmOpValue()
1663 unsigned Value = 0; in getT2AddrModeImm8OffsetOpValue()
1665 if (static_cast<int32_t>(tmp) < 0) in getT2AddrModeImm8OffsetOpValue()
1680 // {3-0} = Rm. in getT2SORegOpValue()
1681 // {4} = 0 in getT2SORegOpValue()
1693 unsigned SBits = 0; in getT2SORegOpValue()
1701 case ARM_AM::lsl: SBits = 0x0; break; in getT2SORegOpValue()
1702 case ARM_AM::lsr: SBits = 0x2; break; in getT2SORegOpValue()
1703 case ARM_AM::asr: SBits = 0x4; break; in getT2SORegOpValue()
1705 case ARM_AM::ror: SBits = 0x6; break; in getT2SORegOpValue()
1726 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); in getBitfieldInvertedMaskOpValue()
1736 // {7-0} = Number of registers in getRegisterListOpValue()
1739 // {15-0} = Bitfield of GPRs. in getRegisterListOpValue()
1744 unsigned Binary = 0; in getRegisterListOpValue()
1749 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; in getRegisterListOpValue()
1750 Binary |= (RegNo & 0x1f) << 8; in getRegisterListOpValue()
1785 unsigned Align = 0; in getAddrMode6AddressOpValue()
1791 case 8: Align = 0x01; break; in getAddrMode6AddressOpValue()
1792 case 16: Align = 0x02; break; in getAddrMode6AddressOpValue()
1793 case 32: Align = 0x03; break; in getAddrMode6AddressOpValue()
1809 unsigned Align = 0; in getAddrMode6OneLane32AddressOpValue()
1815 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. in getAddrMode6OneLane32AddressOpValue()
1816 case 2: Align = 0x00; break; in getAddrMode6OneLane32AddressOpValue()
1817 case 4: Align = 0x03; break; in getAddrMode6OneLane32AddressOpValue()
1836 unsigned Align = 0; in getAddrMode6DupAddressOpValue()
1842 case 8: Align = 0x01; break; in getAddrMode6DupAddressOpValue()
1843 case 16: Align = 0x03; break; in getAddrMode6DupAddressOpValue()
1854 if (MO.getReg() == 0) return 0x0D; in getAddrMode6OffsetOpValue()
1911 support::endian::write<uint16_t>(CB, Binary & 0xffff, Endian); in encodeInstruction()
1934 const MCOperand BranchMO = MI.getOperand(0); in getBFAfterTargetOpValue()
1941 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc())); in getBFAfterTargetOpValue()
1942 return 0; in getBFAfterTargetOpValue()
1959 int Imm = 0; in getVPTMaskOpValue()
1963 unsigned PrevBit = 0; in getVPTMaskOpValue()
1964 for (int i = 3; i >= 0; --i) { in getVPTMaskOpValue()
1968 if ((Value & ~(~0U << i)) == 0) { in getVPTMaskOpValue()
1992 assert(0 && "Unexpected Condition!"); in getRestrictedCondCodeOpValue()
1993 return 0; in getRestrictedCondCodeOpValue()
1996 return 0; in getRestrictedCondCodeOpValue()