Lines Matching defs:MI
88 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
91 unsigned Opcode = MI->getOpcode();
95 const MCOperand &Reg = MI->getOperand(0);
103 const MCOperand &Reg = MI->getOperand(0);
111 const MCOperand &Reg = MI->getOperand(0);
119 const MCOperand &Reg = MI->getOperand(0);
129 const MCOperand &Dst = MI->getOperand(0);
130 const MCOperand &MO1 = MI->getOperand(1);
131 const MCOperand &MO2 = MI->getOperand(2);
132 const MCOperand &MO3 = MI->getOperand(3);
135 printSBitModifierOperand(MI, 6, STI, O);
136 printPredicateOperand(MI, 4, STI, O);
152 const MCOperand &Dst = MI->getOperand(0);
153 const MCOperand &MO1 = MI->getOperand(1);
154 const MCOperand &MO2 = MI->getOperand(2);
157 printSBitModifierOperand(MI, 5, STI, O);
158 printPredicateOperand(MI, 3, STI, O);
180 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
183 printPredicateOperand(MI, 2, STI, O);
187 printRegisterList(MI, 4, STI, O);
194 if (MI->getOperand(2).getReg() == ARM::SP &&
195 MI->getOperand(3).getImm() == -4) {
197 printPredicateOperand(MI, 4, STI, O);
199 printRegName(O, MI->getOperand(1).getReg());
209 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
212 printPredicateOperand(MI, 2, STI, O);
216 printRegisterList(MI, 4, STI, O);
223 if (MI->getOperand(2).getReg() == ARM::SP &&
224 MI->getOperand(4).getImm() == 4) {
226 printPredicateOperand(MI, 5, STI, O);
228 printRegName(O, MI->getOperand(0).getReg());
238 if (MI->getOperand(0).getReg() == ARM::SP) {
240 printPredicateOperand(MI, 2, STI, O);
242 printRegisterList(MI, 4, STI, O);
251 if (MI->getOperand(0).getReg() == ARM::SP) {
253 printPredicateOperand(MI, 2, STI, O);
255 printRegisterList(MI, 4, STI, O);
263 unsigned BaseReg = MI->getOperand(0).getReg();
264 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
265 if (MI->getOperand(i).getReg() == BaseReg)
271 printPredicateOperand(MI, 1, STI, O);
277 printRegisterList(MI, 3, STI, O);
294 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
301 NewMI.addOperand(MI->getOperand(0));
307 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
308 NewMI.addOperand(MI->getOperand(i));
319 switch (MI->getOperand(0).getImm()) {
321 if (!printAliasInstr(MI, Address, STI, O))
322 printInstruction(MI, Address, STI, O);
335 if (!printAliasInstr(MI, Address, STI, O))
336 printInstruction(MI, Address, STI, O);
341 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
343 const MCOperand &Op = MI->getOperand(OpNo);
381 void ARMInstPrinter::printOperand(const MCInst *MI, uint64_t Address,
384 const MCOperand &Op = MI->getOperand(OpNum);
386 return printOperand(MI, OpNum, STI, O);
387 uint64_t Target = ARM_MC::evaluateBranchTarget(MII.get(MI->getOpcode()),
395 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
398 const MCOperand &MO1 = MI->getOperand(OpNum);
426 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
429 const MCOperand &MO1 = MI->getOperand(OpNum);
430 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
431 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
446 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
449 const MCOperand &MO1 = MI->getOperand(OpNum);
450 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
463 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
466 const MCOperand &MO1 = MI->getOperand(Op);
467 const MCOperand &MO2 = MI->getOperand(Op + 1);
468 const MCOperand &MO3 = MI->getOperand(Op + 2);
494 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
497 const MCOperand &MO1 = MI->getOperand(Op);
498 const MCOperand &MO2 = MI->getOperand(Op + 1);
508 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
511 const MCOperand &MO1 = MI->getOperand(Op);
512 const MCOperand &MO2 = MI->getOperand(Op + 1);
523 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
526 const MCOperand &MO1 = MI->getOperand(Op);
529 printOperand(MI, Op, STI, O);
534 const MCOperand &MO3 = MI->getOperand(Op + 2);
539 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
542 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
546 const MCOperand &MO1 = MI->getOperand(OpNum);
547 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
568 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
571 const MCOperand &MO1 = MI->getOperand(Op);
572 const MCOperand &MO2 = MI->getOperand(Op + 1);
573 const MCOperand &MO3 = MI->getOperand(Op + 2);
598 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
601 const MCOperand &MO1 = MI->getOperand(Op);
603 printOperand(MI, Op, STI, O);
607 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
610 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
613 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
617 const MCOperand &MO1 = MI->getOperand(OpNum);
618 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
632 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
635 const MCOperand &MO = MI->getOperand(OpNum);
641 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
644 const MCOperand &MO1 = MI->getOperand(OpNum);
645 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
651 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
654 const MCOperand &MO = MI->getOperand(OpNum);
661 void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
664 const MCOperand &MO1 = MI->getOperand(OpNum);
665 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
679 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
683 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
688 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
691 const MCOperand &MO1 = MI->getOperand(OpNum);
692 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
695 printOperand(MI, OpNum, STI, O);
714 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
717 const MCOperand &MO1 = MI->getOperand(OpNum);
718 const MCOperand &MO2 = MI->getOperand(OpNum+1);
721 printOperand(MI, OpNum, STI, O);
740 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
743 const MCOperand &MO1 = MI->getOperand(OpNum);
744 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
755 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
758 const MCOperand &MO1 = MI->getOperand(OpNum);
765 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
769 const MCOperand &MO = MI->getOperand(OpNum);
778 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
782 const MCOperand &MO = MI->getOperand(OpNum);
792 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
795 unsigned val = MI->getOperand(OpNum).getImm();
799 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
802 unsigned val = MI->getOperand(OpNum).getImm();
806 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
809 unsigned val = MI->getOperand(OpNum).getImm();
813 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
816 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
828 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
831 unsigned Imm = MI->getOperand(OpNum).getImm();
839 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
842 unsigned Imm = MI->getOperand(OpNum).getImm();
851 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
854 if (MI->getOpcode() != ARM::t2CLRM) {
855 assert(is_sorted(drop_begin(*MI, OpNum),
863 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
866 printRegName(O, MI->getOperand(i).getReg());
871 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
874 unsigned Reg = MI->getOperand(OpNum).getReg();
880 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
883 const MCOperand &Op = MI->getOperand(OpNum);
890 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
892 const MCOperand &Op = MI->getOperand(OpNum);
896 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
898 const MCOperand &Op = MI->getOperand(OpNum);
908 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
911 const MCOperand &Op = MI->getOperand(OpNum);
916 unsigned Opcode = MI->getOpcode();
990 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
993 uint32_t Banked = MI->getOperand(OpNum).getImm();
1004 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
1007 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1016 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1018 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
1021 printMandatoryPredicateOperand(MI, OpNum, STI, O);
1024 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1028 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1032 void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
1036 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1040 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1043 if (MI->getOperand(OpNum).getReg()) {
1044 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1050 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1053 O << MI->getOperand(OpNum).getImm();
1056 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1059 O << "p" << MI->getOperand(OpNum).getImm();
1062 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1065 O << "c" << MI->getOperand(OpNum).getImm();
1068 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1071 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1074 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1080 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1083 const MCOperand &MO = MI->getOperand(OpNum);
1101 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1105 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);
1108 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1111 unsigned Imm = MI->getOperand(OpNum).getImm();
1115 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1119 unsigned Mask = MI->getOperand(OpNum).getImm();
1130 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1133 const MCOperand &MO1 = MI->getOperand(Op);
1134 const MCOperand &MO2 = MI->getOperand(Op + 1);
1137 printOperand(MI, Op, STI, O);
1151 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1156 const MCOperand &MO1 = MI->getOperand(Op);
1157 const MCOperand &MO2 = MI->getOperand(Op + 1);
1160 printOperand(MI, Op, STI, O);
1174 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1178 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1181 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1185 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1188 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1192 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1195 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1198 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1205 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1208 const MCOperand &MO1 = MI->getOperand(OpNum);
1209 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1221 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1224 const MCOperand &MO1 = MI->getOperand(OpNum);
1225 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1228 printOperand(MI, OpNum, STI, O);
1252 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1256 const MCOperand &MO1 = MI->getOperand(OpNum);
1257 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1279 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1283 const MCOperand &MO1 = MI->getOperand(OpNum);
1284 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1287 printOperand(MI, OpNum, STI, O);
1314 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1316 const MCOperand &MO1 = MI->getOperand(OpNum);
1317 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1330 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1332 const MCOperand &MO1 = MI->getOperand(OpNum);
1345 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1347 const MCOperand &MO1 = MI->getOperand(OpNum);
1362 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1366 const MCOperand &MO1 = MI->getOperand(OpNum);
1367 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1368 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1387 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1390 const MCOperand &MO = MI->getOperand(OpNum);
1394 void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
1397 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1406 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1409 unsigned Imm = MI->getOperand(OpNum).getImm();
1413 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1416 unsigned Imm = MI->getOperand(OpNum).getImm();
1424 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1427 MCOperand Op = MI->getOperand(OpNum);
1431 return printOperand(MI, OpNum, STI, O);
1437 switch (MI->getOpcode()) {
1440 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1466 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1468 markup(O, Markup::Immediate) << "#" << 16 - MI->getOperand(OpNum).getImm();
1471 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1473 markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
1476 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1479 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1482 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1486 printRegName(O, MI->getOperand(OpNum).getReg());
1490 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1493 unsigned Reg = MI->getOperand(OpNum).getReg();
1503 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1506 unsigned Reg = MI->getOperand(OpNum).getReg();
1516 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1523 printRegName(O, MI->getOperand(OpNum).getReg());
1525 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1527 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1531 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1538 printRegName(O, MI->getOperand(OpNum).getReg());
1540 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1542 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1544 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1548 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1553 printRegName(O, MI->getOperand(OpNum).getReg());
1557 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1561 unsigned Reg = MI->getOperand(OpNum).getReg();
1571 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1579 printRegName(O, MI->getOperand(OpNum).getReg());
1581 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1583 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1587 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1595 printRegName(O, MI->getOperand(OpNum).getReg());
1597 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1599 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1601 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1606 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1608 unsigned Reg = MI->getOperand(OpNum).getReg();
1619 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1625 printRegName(O, MI->getOperand(OpNum).getReg());
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1629 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1634 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1640 printRegName(O, MI->getOperand(OpNum).getReg());
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1646 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1650 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1658 printRegName(O, MI->getOperand(OpNum).getReg());
1660 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1662 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1666 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1673 printRegName(O, MI->getOperand(OpNum).getReg());
1675 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1677 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1679 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1684 void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1687 unsigned Reg = MI->getOperand(OpNum).getReg();
1698 void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1701 unsigned Val = MI->getOperand(OpNo).getImm();
1705 void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
1708 ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1713 void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1717 unsigned Mask = MI->getOperand(OpNum).getImm();
1729 void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
1732 uint32_t Val = MI->getOperand(OpNum).getImm();