Lines Matching +full:8 +full:v
105 /// the 8-bit imm value.
109 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; }
116 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
123 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
150 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
161 return llvm::rotl<uint32_t>(Arg, RotAmt) | ((RotAmt >> 1) << 8);
166 inline bool isSOImmTwoPartVal(unsigned V) {
168 V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
169 if (V == 0)
173 V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
174 return V == 0;
177 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
179 inline unsigned getSOImmTwoPartFirst(unsigned V) {
180 return llvm::rotr<uint32_t>(255U, getSOImmValRotate(V)) & V;
183 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
185 inline unsigned getSOImmTwoPartSecond(unsigned V) {
187 V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
190 assert(V == (llvm::rotr<uint32_t>(255U, getSOImmValRotate(V)) & V));
191 return V;
195 /// by two SOImmVal, that -V = First + Second.
196 /// "R+V" can be optimized to (sub (sub R, First), Second).
197 /// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
198 inline bool isSOImmTwoPartValNeg(unsigned V) {
200 if (!isSOImmTwoPartVal(-V))
203 First = getSOImmTwoPartFirst(-V);
208 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
211 // 8-bit (or less) immediates are trivially immediate operand with a shift
220 /// by left shifting a 8-bit immediate.
221 inline bool isThumbImmShiftedVal(unsigned V) {
223 V = (~255U << getThumbImmValShift(V)) & V;
224 return V == 0;
240 inline bool isThumbImm16ShiftedVal(unsigned V) {
242 V = (~65535U << getThumbImm16ValShift(V)) & V;
243 return V == 0;
246 /// getThumbImmNonShiftedVal - If V is a value that satisfies
248 inline unsigned getThumbImmNonShiftedVal(unsigned V) {
249 return V >> getThumbImmValShift(V);
254 /// if the specified value can be obtained by splatting the low 8 bits
262 inline int getT2SOImmValSplatVal(unsigned V) {
265 if ((V & 0xffffff00) == 0)
266 return V;
269 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
270 // Any passing value only has 8 bits of payload, splatted across the word
277 return (((Vs == V) ? 1 : 2) << 8) | Imm;
280 if (Vs == (u | (u << 8)))
281 return (3 << 8) | Imm;
287 /// specified value is a rotated 8-bit value. Return -1 if no rotation
290 inline int getT2SOImmValRotateVal(unsigned V) {
291 unsigned RotAmt = llvm::countl_zero(V);
296 if ((llvm::rotr<uint32_t>(0xff000000U, RotAmt) & V) == V)
297 return (llvm::rotr<uint32_t>(V, 24 - RotAmt) & 0x7f) |
298 ((RotAmt + 8) << 7);
308 // If 'Arg' is an 8-bit splat, then get the encoded value.
321 inline unsigned getT2SOImmValRotate(unsigned V) {
322 if ((V & ~255U) == 0) return 0;
324 unsigned RotAmt = llvm::countr_zero(V);
329 unsigned V = Imm;
333 if (getT2SOImmValSplatVal(V) != -1)
335 V = llvm::rotr<uint32_t>(~255U, getT2SOImmValRotate(V)) & V;
336 if (V == 0)
340 if (getT2SOImmVal(V) != -1) return true;
343 V = Imm;
344 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
345 V &= ~0xff00ff00U;
346 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
347 V &= ~0x00ff00ffU;
349 if (getT2SOImmVal(V) != -1) return true;
359 unsigned V = llvm::rotr<uint32_t>(~255, getT2SOImmValRotate(Imm)) & Imm;
361 if (getT2SOImmVal(V) != -1) return V;
428 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
435 return ((int)isSub << 8) | Offset | (IdxMode << 9);
439 return ((AM3Opc >> 8) & 1) ? sub : add;
473 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
478 return ((int)isSub << 8) | Offset;
482 return ((AM5Opc >> 8) & 1) ? sub : add;
494 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
499 return ((int)isSub << 8) | Offset;
505 return ((AM5Opc >> 8) & 1) ? sub : add;
528 // represented here as encoded integers. The low 8 bits hold the immediate
529 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
534 return (OpCmode << 8) | Val;
537 return (ModImm >> 8) & 0x1f;
550 // 8-bit vector elements
552 EltBits = 8;
556 Val = Imm8 << (8 * ByteNum);
561 Val = Imm8 << (8 * ByteNum);
566 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
570 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
572 Val |= (uint64_t)0xff << (8 * ByteNum);
587 Value >>= 8;
604 Value = (Value >> 8) | 0xa00;
620 Value = (Value >> 8) | 0x200;
632 // We expect an 8-bit binary encoding of a floating-point number here.
638 // 8-bit FP IEEE Float Encoding
651 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
652 /// floating-point value. If the value cannot be represented as an 8-bit
677 /// If this is a FP16Imm encoded as a fp32 value, return the 8-bit encoding
689 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
690 /// floating-point value. If the value cannot be represented as an 8-bit
717 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
718 /// floating-point value. If the value cannot be represented as an 8-bit