Lines Matching defs:imm
1669 unsigned imm = fieldFromInstruction(Val, 7, 5);
1691 if (Shift == ARM_AM::ror && imm == 0)
1694 unsigned Op = Shift | (imm << 3);
1871 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1987 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1988 Inst.addOperand(MCOperand::createImm(imm));
2006 imm |= U << 8;
2011 Inst.addOperand(MCOperand::createImm(imm));
2050 unsigned imm = fieldFromInstruction(Insn, 0, 12);
2133 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
2135 Inst.addOperand(MCOperand::createImm(imm));
2138 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
2156 unsigned imm = fieldFromInstruction(Val, 7, 5);
2175 if (ShOp == ARM_AM::ror && imm == 0)
2184 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2186 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2214 unsigned imm = fieldFromInstruction(Insn, 8, 4);
2384 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2648 int imm = fieldFromInstruction(Insn, 0, 8);
2650 if(imm > 4) return MCDisassembler::Fail;
2652 Inst.addOperand(MCOperand::createImm(imm));
2661 unsigned imm = fieldFromInstruction(Insn, 0, 8);
2665 if (imm == 0x0D) {
2667 } else if (imm == 0x1D) {
2669 } else if (imm == 0x2D) {
2671 } else if (imm == 0x0F) {
2677 Inst.addOperand(MCOperand::createImm(imm));
2689 unsigned imm = 0;
2691 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2692 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2693 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2694 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2702 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2703 Inst.addOperand(MCOperand::createImm(imm));
2715 unsigned imm = 0;
2717 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2718 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2727 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2728 Inst.addOperand(MCOperand::createImm(imm));
2822 unsigned imm = fieldFromInstruction(Val, 0, 12);
2828 if (!add) imm *= -1;
2829 if (imm == 0 && !add) imm = INT32_MIN;
2830 Inst.addOperand(MCOperand::createImm(imm));
2832 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2843 // U == 1 to add imm, 0 to subtract it.
2845 unsigned imm = fieldFromInstruction(Val, 0, 8);
2851 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2853 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2864 // U == 1 to add imm, 0 to subtract it.
2866 unsigned imm = fieldFromInstruction(Val, 0, 8);
2872 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2874 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2918 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2922 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2923 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2925 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2929 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2931 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
3756 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3757 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3758 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3759 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3760 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3771 Inst.addOperand(MCOperand::createImm(imm));
3803 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3804 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3805 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3806 imm |= cmode << 8;
3807 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3815 Inst.addOperand(MCOperand::createImm(imm));
3941 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3956 Inst.addOperand(MCOperand::createImm(imm));
4009 unsigned imm = fieldFromInstruction(Val, 3, 5);
4013 Inst.addOperand(MCOperand::createImm(imm));
4021 unsigned imm = Val << 2;
4023 Inst.addOperand(MCOperand::createImm(imm));
4024 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
4045 unsigned imm = fieldFromInstruction(Val, 0, 2);
4063 Inst.addOperand(MCOperand::createImm(imm));
4160 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4161 imm |= (U << 8);
4162 imm |= (Rn << 9);
4232 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4244 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4245 imm |= (Rn << 13);
4313 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4324 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4325 imm |= (Rn << 9);
4352 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4364 int imm = fieldFromInstruction(Insn, 0, 12);
4401 if (imm == 0)
4402 imm = INT32_MIN;
4404 imm = -imm;
4406 Inst.addOperand(MCOperand::createImm(imm));
4416 int imm = Val & 0xFF;
4418 if (!(Val & 0x100)) imm *= -1;
4419 Inst.addOperand(MCOperand::createImm(imm * 4));
4430 int imm = Val & 0x7F;
4433 imm *= -1;
4434 Inst.addOperand(MCOperand::createImm(imm * 4));
4446 unsigned imm = fieldFromInstruction(Val, 0, 9);
4450 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4462 unsigned imm = fieldFromInstruction(Val, 0, 8);
4466 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4478 unsigned imm = fieldFromInstruction(Val, 0, 8);
4483 Inst.addOperand(MCOperand::createImm(imm));
4490 int imm = Val & 0xFF;
4492 imm = INT32_MIN;
4494 imm *= -1;
4495 Inst.addOperand(MCOperand::createImm(imm));
4503 int imm = Val & 0x7F;
4505 imm = INT32_MIN;
4507 imm *= -1;
4508 if (imm != INT32_MIN)
4509 imm *= (1U << shift);
4510 Inst.addOperand(MCOperand::createImm(imm));
4521 unsigned imm = fieldFromInstruction(Val, 0, 9);
4548 imm |= 0x100;
4556 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4569 unsigned imm = fieldFromInstruction(Val, 0, 8);
4573 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4586 unsigned imm = fieldFromInstruction(Val, 0, 8);
4592 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4666 unsigned imm = fieldFromInstruction(Val, 0, 12);
4682 Inst.addOperand(MCOperand::createImm(imm));
4690 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4694 Inst.addOperand(MCOperand::createImm(imm));
4772 int imm = fieldFromInstruction(Insn, 0, 7);
4778 if (imm == 0)
4779 imm = INT32_MIN; // indicate -0
4781 imm *= -1;
4783 if (imm != INT32_MIN)
4784 imm *= (1U << shift);
4785 Inst.addOperand(MCOperand::createImm(imm));
4871 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4872 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4897 unsigned imm = fieldFromInstruction(Val, 0, 8);
4900 Inst.addOperand(MCOperand::createImm(imm));
4903 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4906 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4909 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4910 (imm << 8) | imm));
4916 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
4917 Inst.addOperand(MCOperand::createImm(imm));
5148 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5149 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5150 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5159 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5174 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5175 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5176 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5187 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5202 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5203 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5204 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5213 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5228 unsigned imm = fieldFromInstruction(Insn, 0, 12);
5229 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
5230 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
5239 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
6022 unsigned imm = fieldFromInstruction(Insn, 16, 6);
6028 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6029 if (!(imm & 0x38)) {
6060 if (!(imm & 0x20)) return MCDisassembler::Fail;
6066 Inst.addOperand(MCOperand::createImm(64 - imm));
6081 unsigned imm = fieldFromInstruction(Insn, 16, 6);
6087 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6088 if (!(imm & 0x38)) {
6119 if (!(imm & 0x20)) return MCDisassembler::Fail;
6125 Inst.addOperand(MCOperand::createImm(64 - imm));