Lines Matching defs:Rm
1667 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1672 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1705 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2049 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2154 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2212 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2245 if (type && Rm == 15)
2259 if (!type && Rm == 15)
2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2289 if (!type && Rm == 15)
2307 if (!type && (Rt == 15 || Rm == 15))
2384 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2433 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2442 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2743 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2772 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2947 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3184 // The fixed offset encodes as Rm == 0xd, so we check for that.
3185 if (Rm == 0xd) {
3215 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3216 // variant encodes Rm == 0xf. Anything else is a register offset post-
3218 if (Rm != 0xD && Rm != 0xF &&
3219 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3302 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3356 if (Rm == 0xF)
3386 if (Rm == 0xD)
3388 else if (Rm != 0xF) {
3389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3571 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3592 if (Rm != 0xF) {
3601 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3602 // variant encodes Rm == 0xf. Anything else is a register offset post-
3604 if (Rm != 0xD && Rm != 0xF &&
3605 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3619 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3645 if (Rm != 0xF)
3652 if (Rm != 0xD && Rm != 0xF) {
3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3668 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3677 if (Rm != 0xF) {
3686 if (Rm == 0xD)
3688 else if (Rm != 0xF) {
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3704 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3730 if (Rm != 0xF) {
3739 if (Rm == 0xD)
3741 else if (Rm != 0xF) {
3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3857 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3858 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3907 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3908 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3929 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3993 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3997 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
4044 unsigned Rm = fieldFromInstruction(Val, 2, 4);
4061 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4714 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4741 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4744 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4839 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
5178 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5181 if (Rm == 0xF) S = MCDisassembler::SoftFail;
5252 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5292 if (Rm != 0xF) { // Writeback
5299 if (Rm != 0xF) {
5300 if (Rm != 0xD) {
5301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5319 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5357 if (Rm != 0xF) { // Writeback
5364 if (Rm != 0xF) {
5365 if (Rm != 0xD) {
5366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5384 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5422 if (Rm != 0xF) { // Writeback
5429 if (Rm != 0xF) {
5430 if (Rm != 0xD) {
5431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5451 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5485 if (Rm != 0xF) { // Writeback
5492 if (Rm != 0xF) {
5493 if (Rm != 0xD) {
5494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5514 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5553 if (Rm != 0xF) { // Writeback
5560 if (Rm != 0xF) {
5561 if (Rm != 0xD) {
5562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5584 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5616 if (Rm != 0xF) { // Writeback
5623 if (Rm != 0xF) {
5624 if (Rm != 0xD) {
5625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5647 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5695 if (Rm != 0xF) { // Writeback
5702 if (Rm != 0xF) {
5703 if (Rm != 0xD) {
5704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5728 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5767 if (Rm != 0xF) { // Writeback
5774 if (Rm != 0xF) {
5775 if (Rm != 0xD) {
5776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5800 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5802 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5807 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5809 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5826 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5828 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5830 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5837 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5839 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
6169 unsigned Rm = fieldFromInstruction(Val, 0, 4);
6170 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
6182 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
6852 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6883 // Rm, the amount to shift by
6884 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6890 if (Rda == Rm)
6911 // Rm, the amount to shift by
6912 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6960 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6961 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))