Lines Matching defs:ShiftTy

901     ARM_AM::ShiftOpc ShiftTy;
911     ARM_AM::ShiftOpc ShiftTy;
918     ARM_AM::ShiftOpc ShiftTy;
1480     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
2611       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2622       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
3363                                      PostIdxReg.ShiftTy);
3720     Op->RegShiftedReg.ShiftTy = ShTy;
3734     Op->RegShiftedImm.ShiftTy = ShTy;
3906   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3911     Op->PostIdxReg.ShiftTy = ShiftTy;
4053     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
4054       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
4076        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
4081        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4303   auto ShiftTy = ShiftTyOpt.value();
4319   if (ShiftTy == ARM_AM::rrx) {
4346           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4347           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4354         ShiftTy = ARM_AM::lsl;
4370   if (ShiftReg && ShiftTy != ARM_AM::rrx)
4372         ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc, *this));
4374     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
5684   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5688     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5696       ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E, *this));
6173     // If <ShiftTy> #0, turn it into a no_shift.
10494     ARM_AM::ShiftOpc ShiftTy;
10497     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
10498     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
10499     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
10500     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
10502     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10519     ARM_AM::ShiftOpc ShiftTy;
10522     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
10523     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
10524     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
10525     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
10531     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10533     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);