Lines Matching defs:ShiftImm

892     unsigned ShiftImm;        // shift for OffsetReg.
902     unsigned ShiftImm;
914     unsigned ShiftImm;
920     unsigned ShiftImm;
1722         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1741     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1920         (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2611       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2620     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
3025                             Memory.ShiftImm, Memory.ShiftType);
3267                         Memory.ShiftImm, Memory.ShiftType);
3277     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3362     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3717                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E,
3723     Op->RegShiftedReg.ShiftImm = ShiftImm;
3731                          unsigned ShiftImm, SMLoc S, SMLoc E,
3736     Op->RegShiftedImm.ShiftImm = ShiftImm;
3888             ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3896     Op->Memory.ShiftImm = ShiftImm;
3907                    unsigned ShiftImm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3912     Op->PostIdxReg.ShiftImm = ShiftImm;
4044       OS << " shift-imm:" << Memory.ShiftImm;
4055          << PostIdxReg.ShiftImm;
4082        << RegShiftedImm.ShiftImm << ">";
5685   unsigned ShiftImm = 0;
5688     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5696       ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E, *this));
6091   unsigned ShiftImm = 0;
6094     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
6105                                            ShiftType, ShiftImm, 0, isNegative,