Lines Matching defs:Operands
438 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
441 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
518 bool CarrySetting, OperandVector &Operands,
521 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands,
665 OperandVector &Operands,
669 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands,
671 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, bool Load,
716 SMLoc NameLoc, OperandVector &Operands) override;
724 const OperandVector &Operands) override;
727 OperandVector &Operands, MCStreamer &Out,
730 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
744 SMLoc IDLoc, OperandVector &Operands);
746 OperandVector &Operands);
4152 static unsigned getMnemonicOpsEndInd(const OperandVector &Operands) {
4156 if (Operands[0]->isToken() &&
4157 static_cast<ARMOperand &>(*Operands[0]).getToken() == "cps") {
4158 if (Operands.size() > 1 && Operands[1]->isImm() &&
4159 static_cast<ARMOperand &>(*Operands[1]).getImm()->getKind() ==
4162 static_cast<ARMOperand &>(*Operands[1]).getImm())
4165 static_cast<ARMOperand &>(*Operands[1]).getImm())
4172 while (MnemonicOpsEndInd < Operands.size()) {
4173 auto Op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
4296 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4311 (ARMOperand *)Operands.pop_back_val().release());
4371 Operands.push_back(ARMOperand::CreateShiftedRegister(
4374 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4386 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4394 Operands.push_back(
4399 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4425 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), SIdx, E,
4482 ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4493 Operands.push_back(
4502 ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4516 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S, *this));
4523 ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4535 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S, *this));
4541 ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4566 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E, *this));
4611 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
4769 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E, *this));
4773 Operands.push_back(
4826 ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) {
4847 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
4850 Operands.push_back(
4854 Operands.push_back(ARMOperand::CreateVectorListIndexed(
4867 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
4872 Operands.push_back(
4876 Operands.push_back(ARMOperand::CreateVectorListIndexed(
4882 Operands.push_back(ARMOperand::CreateReg(Reg, S, E, *this));
5036 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E, *this));
5040 Operands.push_back(ARMOperand::CreateVectorListIndexed(
5048 ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
5108 Operands.push_back(
5114 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
5127 Operands.push_back(
5134 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
5172 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
5178 ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
5207 Operands.push_back(
5213 ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
5215 if (static_cast<ARMOperand &>(*Operands.back()).isMSRMask() ||
5216 static_cast<ARMOperand &>(*Operands.back()).isBankedReg())
5229 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S, *this));
5245 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S, *this));
5308 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S, *this));
5314 ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5316 if (static_cast<ARMOperand &>(*Operands.back()).isBankedReg() ||
5317 static_cast<ARMOperand &>(*Operands.back()).isMSRMask())
5332 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S, *this));
5339 ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands,
5374 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc, *this));
5379 ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5393 Operands.push_back(ARMOperand::CreateImm(
5403 ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5449 Operands.push_back(
5458 ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) {
5491 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc, *this));
5496 ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) {
5541 Operands.push_back(ARMOperand::CreateModImm(
5553 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1, *this));
5557 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5559 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1, *this));
5593 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2, *this));
5603 ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) {
5648 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc, *this));
5653 ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5695 Operands.push_back(
5701 ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5737 Operands.push_back(ARMOperand::CreateImm(
5762 Operands.push_back(ARMOperand::CreatePostIdxReg(
5769 unsigned findCondCodeInd(const OperandVector &Operands,
5772 auto Op = static_cast<ARMOperand &>(*Operands[I]);
5779 unsigned findCCOutInd(const OperandVector &Operands,
5782 auto Op = static_cast<ARMOperand &>(*Operands[I]);
5793 const OperandVector &Operands) {
5794 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5795 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5796 unsigned CondOutI = findCCOutInd(Operands, MnemonicOpsEndInd);
5803 if (Operands.size() == MnemonicOpsEndInd + 3) {
5806 if (((ARMOperand &)*Operands[RegRd]).getReg() ==
5807 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 1]).getReg()) {
5817 ((ARMOperand &)*Operands[RegRd]).addRegOperands(Inst, 1);
5820 ((ARMOperand &)*Operands[CondOutI]).addCCOutOperands(Inst, 1);
5823 *ARMOperand::CreateCCOut(0, Operands[0]->getEndLoc(), *this);
5827 ((ARMOperand &)*Operands[RegRn]).addRegOperands(Inst, 1);
5829 ((ARMOperand &)*Operands[RegRm]).addRegOperands(Inst, 1);
5833 ((ARMOperand &)*Operands[CondI]).addCondCodeOperands(Inst, 2);
5836 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5842 const OperandVector &Operands) {
5843 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5844 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5847 : static_cast<ARMOperand &>(*Operands[CondI]).getCondCode());
5875 ARMOperand &op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
5882 ARMOperand &op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
5888 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addImmOperands(Inst, 1);
5890 ((ARMOperand &)*Operands[CondI]).addCondCodeOperands(Inst, 2);
5893 llvm::ARMCC::AL, Operands[0]->getEndLoc(), *this);
5899 MCInst &Inst, const OperandVector &Operands) {
5901 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
5902 unsigned CondI = findCondCodeInd(Operands, MnemonicOpsEndInd);
5905 assert(Operands.size() == MnemonicOpsEndInd + 6);
5907 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addRegOperands(Inst, 1); // Rt
5908 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 1])
5910 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 2])
5912 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 3])
5914 // skip second copy of Qd in Operands[6]
5915 ((ARMOperand &)*Operands[MnemonicOpsEndInd + 5])
5918 ((ARMOperand &)*Operands[CondI])
5922 *ARMOperand::CreateCondCode(ARMCC::AL, Operands[0]->getEndLoc(), *this);
5929 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5952 Operands.push_back(ARMOperand::CreateMem(
5958 Operands.push_back(
6009 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
6016 Operands.push_back(
6053 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, AdjustedOffset, 0,
6066 Operands.push_back(
6104 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
6111 Operands.push_back(
6186 ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) {
6187 LLVM_DEBUG(dbgs() << "PARSE FPImm, Ops: " << Operands.size());
6217 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
6219 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[I]);
6228 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6250 Operands.push_back(
6265 Operands.push_back(
6276 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
6282 ParseStatus ResTy = MatchOperandParserImpl(Operands, Mnemonic);
6301 if (!tryParseRegisterWithWriteBack(Operands))
6303 int Res = tryParseShiftRegister(Operands);
6313 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S, *this));
6333 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E, *this));
6337 return parseMemory(Operands);
6340 return parseRegisterList(Operands, !Mnemonic.starts_with("clr"), false,
6377 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E, *this));
6383 Operands.push_back(ARMOperand::CreateToken(
6409 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E, *this));
6424 Operands.push_back(
6744 bool operandsContainWide(OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6746 auto &Op = static_cast<ARMOperand &>(*Operands[I]);
6759 OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6761 if (operandsContainWide(Operands, MnemonicOpsEndInd))
6763 if (Operands.size() != MnemonicOpsEndInd + 3)
6766 const auto &Op3 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
6767 auto &Op4 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
6778 auto &Op5 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]);
6838 Operands.erase(Operands.begin() + MnemonicOpsEndInd);
6864 StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) {
6865 if (!hasMVE() || Operands.size() <= MnemonicOpsEndInd)
6878 for (auto &Operand : Operands) {
6890 for (auto &Operand : Operands) {
6923 OperandVector &Operands,
6933 if (Operands.size() < IdX + 2)
6936 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[IdX]);
6937 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[IdX + 1]);
6961 Operands.insert(Operands.begin() + IdX + 1,
6972 OperandVector &Operands,
6976 if (Operands.size() < 3 + MnemonicOpsEndInd)
6982 const MCParsedAsmOperand &Op2 = *Operands[MnemonicOpsEndInd + 1];
7017 const MCParsedAsmOperand &Op3 = *Operands[MnemonicOpsEndInd + 2];
7021 Operands.erase(Operands.begin() + MnemonicOpsEndInd + 2);
7022 Operands[MnemonicOpsEndInd + 1] =
7027 void removeCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7029 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) {
7030 Operands.erase(Operands.begin() + I);
7036 void removeCCOut(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7038 if (static_cast<ARMOperand &>(*Operands[I]).isCCOut()) {
7039 Operands.erase(Operands.begin() + I);
7045 void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
7047 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) {
7048 Operands.erase(Operands.begin() + I);
7056 SMLoc NameLoc, OperandVector &Operands) {
7096 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc, *this));
7128 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc, *this));
7168 Operands.push_back(
7176 Operands.push_back(ARMOperand::CreateCondCode(
7188 Operands.push_back(ARMOperand::CreateVPTPred(
7194 Operands.push_back(ARMOperand::CreateImm(
7225 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc, *this));
7232 unsigned MnemonicOpsEndInd = Operands.size();
7237 if (parseOperand(Operands, Mnemonic)) {
7243 if (parseOperand(Operands, Mnemonic)) {
7253 Operands, MnemonicOpsEndInd);
7265 CDEConvertDualRegOperand(Mnemonic, Operands, MnemonicOpsEndInd);
7272 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7278 Operands.erase(Operands.begin() + 1);
7279 Operands.erase(Operands.begin());
7283 Operands.insert(Operands.begin(),
7285 Operands.insert(Operands.begin(), ARMOperand::CreateToken(
7288 !shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7294 Operands.erase(Operands.begin() + 1);
7295 Operands.erase(Operands.begin());
7299 Operands.insert(Operands.begin(),
7301 Operands.insert(Operands.begin(),
7304 !shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7309 removeCondCode(Operands, MnemonicOpsEndInd);
7310 Operands.erase(Operands.begin());
7312 Operands.insert(Operands.begin(), ARMOperand::CreateToken(
7318 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7328 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd - 2]);
7330 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd - 1]);
7333 Operands.erase(Operands.begin());
7338 Operands.insert(Operands.begin(),
7345 Operands.insert(Operands.begin() + 1,
7354 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands,
7356 removeVPTCondCode(Operands, MnemonicOpsEndInd);
7363 for (unsigned I = 1; I < Operands.size(); ++I)
7364 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7375 Operands.erase(Operands.begin());
7376 Operands.insert(Operands.begin(),
7387 Operands.size() == MnemonicOpsEndInd + 1 &&
7388 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).isImm())
7389 removeCondCode(Operands, MnemonicOpsEndInd);
7392 fixupGNULDRDAlias(Mnemonic, Operands, MnemonicOpsEndInd);
7402 if (!isThumb() && Operands.size() > MnemonicOpsEndInd + 1 + (!IsLoad) &&
7406 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7407 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7431 Operands[Idx] = ARMOperand::CreateReg(NewReg, Op1.getStartLoc(),
7433 Operands.erase(Operands.begin() + Idx + 1);
7443 Operands.size() == MnemonicOpsEndInd + 3 &&
7444 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).isReg() &&
7445 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]).getReg() ==
7447 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]).isReg() &&
7448 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]).getReg() ==
7450 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]).isImm()) {
7451 Operands.front() = ARMOperand::CreateToken(Name, NameLoc, *this);
7452 removeCCOut(Operands, MnemonicOpsEndInd);
7497 unsigned getRegListInd(const OperandVector &Operands,
7499 for (unsigned I = MnemonicOpsEndInd; I < Operands.size(); ++I) {
7500 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[I]);
7509 const OperandVector &Operands,
7518 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7522 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7528 const OperandVector &Operands,
7536 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7540 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7544 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
7549 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
7559 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7564 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7570 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7573 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7583 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7592 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7596 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7634 const OperandVector &Operands,
7637 SMLoc Loc = Operands[0]->getStartLoc();
7650 SMLoc CondLoc = Operands[0]->getEndLoc();
7651 for (unsigned I = 1; I < Operands.size(); ++I)
7652 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7653 CondLoc = Operands[I]->getStartLoc();
7698 for (unsigned I = 1; I < Operands.size(); ++I)
7699 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7700 PredLoc = Operands[I]->getStartLoc();
7720 if (Operands.size() ==
7723 *Operands[MnemonicOpsEndInd + 1]); // the register list, a dpr_reglist
7757 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ true,
7763 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ true,
7768 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ false,
7774 if (validateLDRDSTRD(Inst, Operands, /*Load*/ true, /*ARMMode*/ false,
7782 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7787 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ true,
7793 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ true,
7799 if (validateLDRDSTRD(Inst, Operands, /*Load*/ false, /*ARMMode*/ false,
7824 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
7837 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7843 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7849 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7868 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7874 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7878 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7896 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7902 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7906 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7919 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7924 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7928 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7941 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7946 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
7950 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
7985 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8029 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8045 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8059 (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8061 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8067 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
8072 Operands[getRegListInd(Operands, MnemonicOpsEndInd)]->getStartLoc(),
8077 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8081 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8094 return Error(Operands.back()->getStartLoc(),
8099 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8104 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8112 return Error(Operands.back()->getStartLoc(),
8116 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8119 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 3))
8129 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8137 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8146 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8148 if (validatetLDMRegList(Inst, Operands, MnemonicOpsEndInd, 2, !isMClass()))
8156 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8158 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 2))
8167 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8173 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8177 if (validatetSTMRegList(Inst, Operands, MnemonicOpsEndInd, 4))
8186 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8197 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8203 if (!(static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]))
8205 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8209 int op = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8211 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]);
8215 return Error(Operands[op]->getStartLoc(), "branch target out of range");
8220 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8222 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8226 int Op = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8228 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
8229 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
8234 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8236 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8251 int i = (Operands[MnemonicOpsEndInd]->isImm()) ? MnemonicOpsEndInd
8253 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
8267 MCParsedAsmOperand &Op = *Operands[MnemonicOpsEndInd + 1];
8275 MCParsedAsmOperand &Op = *Operands[MnemonicOpsEndInd];
8289 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
8293 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
8302 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8305 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8310 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8312 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8315 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8317 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8323 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd])
8326 return Error(Operands[1]->getStartLoc(),
8329 if (!static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8331 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8342 Operands[3]->getStartLoc(),
8352 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8370 return Error(Operands[1]->getStartLoc(),
8374 return Error(Operands[1]->getStartLoc(),
8384 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8393 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8400 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
8403 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8414 if (Operands[MnemonicOpsEndInd]->getReg() ==
8415 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8416 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8419 if (Operands[MnemonicOpsEndInd]->getReg() ==
8420 Operands[MnemonicOpsEndInd + 2]->getReg()) {
8421 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8431 if (Operands[MnemonicOpsEndInd]->getReg() ==
8432 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8433 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8441 if (Operands[MnemonicOpsEndInd]->getReg() ==
8442 Operands[MnemonicOpsEndInd + 2]->getReg()) {
8443 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8449 if (Operands[MnemonicOpsEndInd + 2]->getReg() !=
8450 Operands[MnemonicOpsEndInd + 4]->getReg())
8451 return Error(Operands[MnemonicOpsEndInd + 2]->getStartLoc(),
8453 if (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 3])
8455 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 5])
8458 return Error(Operands[MnemonicOpsEndInd + 3]->getStartLoc(),
8463 if (Operands[MnemonicOpsEndInd]->getReg() !=
8464 Operands[MnemonicOpsEndInd + 2]->getReg())
8465 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8467 if (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
8469 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 3])
8472 return Error(Operands[MnemonicOpsEndInd + 1]->getStartLoc(),
8478 if (Operands[MnemonicOpsEndInd]->getReg() ==
8479 Operands[MnemonicOpsEndInd + 1]->getReg()) {
8480 return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8554 return Error(Operands[1]->getStartLoc(),
8557 return Error(Operands[1]->getStartLoc(),
8615 // Operands[2] is the coprocessor operand at syntactic level
8617 return Error(Operands[2]->getStartLoc(),
8883 const OperandVector &Operands,
8889 for (auto &Op : Operands) {
8902 if (Operands.size() ==
8905 *Operands[MnemonicOpsEndInd + 1]); // the register list, a dpr_reglist
9232 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1]);
10594 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10612 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10631 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10660 Operands.size() == MnemonicOpsEndInd + 3) {
10671 Operands.size() == MnemonicOpsEndInd + 3) {
10791 (static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
10793 static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 1])
11095 const OperandVector &Operands) {
11101 if (Operands[0]->isToken() &&
11102 static_cast<ARMOperand &>(*Operands[0]).getToken() == "nop" &&
11265 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
11272 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
11278 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
11304 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
11331 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
11355 OperandVector &Operands,
11363 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
11367 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
11377 if (validateInstruction(Inst, Operands, MnemonicOpsEndInd)) {
11390 while (processInstruction(Inst, Operands, MnemonicOpsEndInd, Out))
11417 ReportNearMisses(NearMisses, IDLoc, Operands);
11422 ((ARMOperand &)*Operands[0]).getToken(), FBS);
11424 ((ARMOperand &)*Operands[0]).getLocRange());
12167 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12170 if (parseRegisterList(Operands, true, true) || parseEOL())
12172 ARMOperand &Op = (ARMOperand &)*Operands[0];
12516 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12518 if (parseRegisterList(Operands) || parseEOL())
12520 ARMOperand &Op = (ARMOperand &)*Operands[0];
12558 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12560 if (parseRegisterList(Operands) || parseEOL())
12562 ARMOperand &Op = (ARMOperand &)*Operands[0];
12714 SMLoc IDLoc, OperandVector &Operands) {
12731 unsigned MnemonicOpsEndInd = getMnemonicOpsEndInd(Operands);
12739 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
12842 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[0]);
12845 Message.Loc = Operands[MnemonicOpsEndInd]->getStartLoc();
12863 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
12879 SMLoc IDLoc, OperandVector &Operands) {
12881 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);