Lines Matching defs:Op5
6778 auto &Op5 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd + 2]);
6783 (Op5.isReg() && Op5.getReg() == ARM::PC);
6786 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6788 Op5.isImm() && !Op5.isImm0_508s4());
6807 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6809 const ARMOperand *LastOp = &Op5;
6811 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6837 std::swap(Op4, Op5);