Lines Matching defs:BaseRegNum

886     unsigned BaseRegNum;
1148       if(Memory.BaseRegNum != ARM::PC) return false;
1393     if (Memory.BaseRegNum &&
1394         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1395         !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1406     if (Memory.BaseRegNum &&
1407         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1494             Memory.BaseRegNum))
1506             Memory.BaseRegNum))
1518             Memory.BaseRegNum))
1529     if (Memory.BaseRegNum != ARM::PC)
1736         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1752     return isARMLowRegister(Memory.BaseRegNum) &&
1758         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1771         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1784         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1797         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1835             Memory.BaseRegNum))
1863     if (Memory.BaseRegNum == ARM::PC) return false;
1877         !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1910             Memory.BaseRegNum))
1931             Memory.BaseRegNum))
1970     if (Memory.BaseRegNum == ARM::PC) return false;
2909     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2914     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2919     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2924     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2953     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3003     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3056     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3115     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3144     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3173     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3188     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3194     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3206     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3212     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3226     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3240     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3253     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3259     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3268     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3275     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3282     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3288     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3300     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3311     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3317     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3887   CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
3892     Op->Memory.BaseRegNum = BaseRegNum;
4035     if (Memory.BaseRegNum)
4036       OS << " base:" << RegName(Memory.BaseRegNum);
5938   int BaseRegNum = tryParseRegister();
5939   if (BaseRegNum == -1)
5953         BaseRegNum, nullptr, 0, ARM_AM::no_shift, 0, 0, false, S, E, *this));
6009     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
6053     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, AdjustedOffset, 0,
6104   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,