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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
63 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
64 cl::desc("Inhibit optimization of S->D register accesses on A15"),
68 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
69 cl::desc("Run SimplifyCFG after expanding atomic operations"
70 " to make use of cmpxchg flow-based information"),
74 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
75 cl::desc("Enable ARM load/store optimization pass"),
80 EnableGlobalMerge("arm-global-merge", cl::Hidden,
81 cl::desc("Enable the global merge pass"));
150 // Little endian.
153 // Big endian.
159 Ret += "-p:32:32";
163 Ret += "-Fi8";
167 Ret += "-i64:64";
172 Ret += "-f64:32:64";
177 Ret += "-v64:32:64-v128:32:128";
179 Ret += "-v128:64:128";
182 // particular hardware support on 32-bit ARM).
183 Ret += "-a:0:32";
186 Ret += "-n32";
191 Ret += "-S128";
193 Ret += "-S64";
195 Ret += "-S32";
231 // Default to triple-appropriate float ABI
234 this->Options.FloatABIType = FloatABI::Hard;
236 this->Options.FloatABIType = FloatABI::Soft;
239 // Default to triple-appropriate EABI
251 this->Options.EABIVersion = EABI::GNU;
253 this->Options.EABIVersion = EABI::EABI5;
257 this->Options.TrapUnreachable = true;
258 this->Options.NoTrapAfterNoreturn = true;
282 Attribute CPUAttr = F.getFnAttribute("target-cpu");
283 Attribute FSAttr = F.getFnAttribute("target-features");
295 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
299 FS += FS.empty() ? "+soft-float" : ",+soft-float";
316 if (!I->isThumb() && !I->hasARMOps())
361 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
363 DAG->addMutation(createARMMacroFusionDAGMutation());
371 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
373 DAG->addMutation(createARMMacroFusionDAGMutation());
405 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
408 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
416 return getStandardCSEConfigForOpt(TM->getOptLevel());
420 if (TM->Options.ThreadModel == ThreadModel::Single)
426 // determine whether it succeeded. We can exploit existing control-flow in
428 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
432 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
446 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
450 if (TM->getOptLevel() != CodeGenOptLevel::None)
454 if (TM->getTargetTriple().isOSWindows())
457 if (TM->Options.JMCInstrument)
468 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
473 // to look into using the old value for non-thumb1 code of
477 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
479 // Merging of extern globals is enabled by default on non-Mach-O as we
480 // expect it to be generally either beneficial or harmless. On Mach-O it
483 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
488 if (TM->getOptLevel() != CodeGenOptLevel::None) {
491 // FIXME: IR passes can delete address-taken basic blocks, deleting
493 // address-taken basic blocks which can be invalidated if the function
539 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
564 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
565 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
594 // Don't optimize barriers or block placement at -O0.
606 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
613 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
618 if (TM->getTargetTriple().isOSWindows()) {
642 MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);