Lines Matching +full:use +full:- +full:case
1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
43 #define DEBUG_TYPE "arm-subtarget"
50 UseFusedMulOps("arm-use-mulops",
60 cl::values(clEnumValN(DefaultIT, "arm-default-it",
62 clEnumValN(RestrictedIT, "arm-restrict-it",
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
68 ForceFastISel("arm-force-fast-isel",
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
72 /// so that we can use initializer lists for subtarget initialization.
148 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
164 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
165 // ARMv7k does not use SjLj exception handling.
166 CPUString = "cortex-a7";
187 // Execute only support for >= v8-M Baseline requires movt support
191 report_fatal_error("Cannot generate execute-only code for this target");
210 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
211 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
215 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
222 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
225 // case.
233 case DefaultIT:
236 case RestrictedIT:
241 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
256 case Others:
257 case CortexA5:
259 case CortexA7:
262 case CortexA8:
265 case CortexA9:
269 case CortexA12:
271 case CortexA15:
276 case CortexA17:
277 case CortexA32:
278 case CortexA35:
279 case CortexA53:
280 case CortexA55:
281 case CortexA57:
282 case CortexA72:
283 case CortexA73:
284 case CortexA75:
285 case CortexA76:
286 case CortexA77:
287 case CortexA78:
288 case CortexA78AE:
289 case CortexA78C:
290 case CortexA710:
291 case CortexR4:
292 case CortexR5:
293 case CortexR7:
294 case CortexM3:
295 case CortexM7:
296 case CortexR52:
297 case CortexR52plus:
298 case CortexX1:
299 case CortexX1C:
301 case Exynos:
307 case Kryo:
309 case Krait:
312 case NeoverseV1:
314 case Swift:
352 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
353 // the section that is being relocated. This means we have to use o load even
356 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
363 return isTargetELF() && TM.isPositionIndependent() && !GV->isDSOLocal();
371 // The MachineScheduler can increase register usage, so we use more high
374 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
379 // with the use-misched feature.
391 // with the use-mipipeliner feature.
403 // Thumb1 cores will generally not benefit from post-ra scheduling
424 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
432 // Enable fast-isel for any target, for testing only.
436 // Limit fast-isel to the targets that are or have been tested.
448 // tradeoffs preferred by different sub-architectures and optimisation goals.
451 // 1: r14, r0-r13
452 // 2: r0-r7
453 // 3: r0-r7, r12, lr, r8-r11
455 // callee-saved registers are used later, as they require extra work in the
458 // For thumb1-only targets, only the low registers are allocatable.
462 // Allocate low registers first, so we can select more 16-bit instructions.
464 // with regards to callee-saved registers, because pushing extra registers is
480 // cost per use) so we can use narrow encoding. By default, caller-saved
482 // their cost per use. When optForMinSize, we prefer the low regs even if
490 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() ||
494 return MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF);