Lines Matching full:latency

36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
54 // Subtarget-specific SchedWrite types with map ProcResources and set latency.
56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
59 let Latency = 1 in {
66 def : WriteRes<WriteCMP,   [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
71 let Latency = 2 in {
79 let Latency = 2 in {
82   def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
89   let Latency = 7;
94 def : WriteRes<WriteLd,    [M7UnitLoad]> { let Latency = 1; }
95 def : WriteRes<WritePreLd, [M7UnitLoad]> { let Latency = 2; }
96 def : WriteRes<WriteST,    [M7UnitStore]> { let Latency = 2; }
99 def : WriteRes<WriteBr,    [M7UnitBranch]> { let Latency = 2; }
100 def : WriteRes<WriteBrL,   [M7UnitBranch]> { let Latency = 2; }
101 def : WriteRes<WriteBrTbl, [M7UnitBranch]> { let Latency = 2; }
104 def : WriteRes<WriteNoop, []> { let Latency = 0; }
110 def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
111 def : WriteRes<WriteFPMOV, [M7UnitVPort]>            { let Latency = 3; }
113   let Latency = 3;
116 // The FP pipeline has a latency of 3 cycles.
118 def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]>  { let Latency = 3; }
120   let Latency = 4;
125 def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
127   let Latency = 7;
132 def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
134   let Latency = 11;
138 // Division.   Effective scheduling latency is 3, though real latency is larger
139 def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]>  { let Latency = 16; }
141   let Latency = 30;
145 // Square-root.  Effective scheduling latency is 3; real latency is larger
146 def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
148   let Latency = 30;
190   let Latency = 3;
208     let Latency = 0; // Update is bypassable out of EX1
212     let Latency = 1;
215 def M7SlowLoad : SchedWriteRes<[M7UnitLoad]>            { let Latency = 2; }
217 // Byte and half-word loads should have greater latency than other loads.
292 def M7LoadSP  : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; }
294   let Latency = 2;
352 // Divides are special because they stall for their latency, and so look like a
354 // first, we make the operand latency 1, but keep the instruction latency 7.
361   let Latency = 1;
365   let Latency = 2;
369   let Latency = 1;
373   let Latency = 0;      // Bypassable out of EX1
377   let Latency = 2;
408 // Effective scheduling latency is really 3 for nearly all FP operations,
409 // even if their true latency is higher.
411   let Latency = 3;
415   let Latency = 3;
426 def M7WriteVCMPS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let Latency = 0; }
428   let Latency = 0;
457 // Larger-latency overrides.
470 // making it appear to have 3 cycle latency for scheduling.
476 // Single-precision fused MACs look like latency 5 with advance of 2.
479   let Latency = 5;
489 // it appear to have 3 cycle latency for scheduling.