Lines Matching full:latency

11 // latency and microOps. The naming conventions is to use a prefix, one field
12 // for latency, and one or more microOp count/type designators.
14 //   Latency: #cyc
17 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
26 def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
27 def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
28 def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
36 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
38 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
39 def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;
41 def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;
43 def A57Write_3cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 3;  }
44 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
45 def A57Write_2cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 2;  }
46 def A57Write_3cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 3;  }
47 def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;
49 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
51 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
53 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
55 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
56 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
57 def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
58 def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
63     let Latency = Lat;
70     let Latency = Lat;
74 def A57Write_4cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 4;  }
75 def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
76 def A57Write_4cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 4;  }
77 def A57Write_5cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 5;  }
78 def A57Write_6cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 6;  }
79 def A57Write_6cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 6;  }
80 def A57Write_8cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 8;  }
81 def A57Write_9cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
82 def A57Write_6cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 6;  }
83 def A57Write_6cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 6;  }
90   let Latency     = 64;
96   let Latency     = 6;
101   let Latency     = 6;
106   let Latency     = 7;
111   let Latency     = 8;
116   let Latency     = 9;
120   let Latency     = 9;
124   let Latency     = 8;
128   let Latency     = 6;
132   let Latency     = 6;
136   let Latency     = 6;
141   let Latency     = 5;
146   let Latency     = 5;
150   let Latency     = 5;
154   let Latency     = 5;
159   let Latency     = 10;
163   let Latency     = 10;
168   let Latency     = 1;
173   let Latency     = 1;
178   let Latency     = 1;
183   let Latency     = 2;
188   let Latency     = 3;
193   let Latency     = 1;
198   let Latency     = 2;
203   let Latency     = 3;
208   let Latency     = 6;
213   let Latency     = 2;
217   let Latency     = 2;
221   let Latency     = 2;
225   let Latency     = 36;
231   let Latency     = 3;
236   let Latency     = 4;
243     let Latency = Lat; let NumMicroOps = 2;
249   let Latency     = 3;
254   let Latency     = 3;
259   let Latency     = 4;
263   let Latency     = 3;
270     let Latency = Lat; let NumMicroOps = 2;
275   let Latency     = 4;
284   let Latency     = 10;
289   let Latency     = 2;
295   let Latency     = 3;
301   let Latency     = 3;
307   let Latency     = 4;
311   let Latency     = 4;
317   let Latency     = 8;
323   let Latency     = 9;