Lines Matching defs:isLd
1524 bool isLd = isLoadSingle(Opcode);
1533 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1536 .addReg(MO.getReg(), (isLd ? getDefRegState(true)
1541 } else if (isLd) {
1789 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1790 bool EvenDeadKill = isLd ?
1793 bool OddDeadKill = isLd ?
1807 unsigned NewOpc = (isLd)
1810 if (isLd) {
1814 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1815 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill))
1831 unsigned NewOpc = (isLd)
1836 unsigned NewOpc2 = (isLd)
1841 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {
1843 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1845 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1859 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1862 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1866 if (isLd)
2176 unsigned Base, bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
2218 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
2232 if (I->mayStore() || (!isLd && I->mayLoad()))
2325 bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
2400 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
2407 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
2435 if (isLd) {
2475 if (isLd) {
2571 bool isLd = isLoadSingle(Opc);
2592 if (isLd)