Lines Matching defs:BaseKill

178         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
630     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
704     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
716       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
729     bool KillOldBase = BaseKill &&
777     BaseKill = true; // New base is always killed straight away.
796   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
813        .addReg(Base, getKillRegState(BaseKill));
817     if (!BaseKill)
822     MIB.addReg(Base, getKillRegState(BaseKill));
837     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
907   bool BaseKill = LatestMI->killsRegister(Base, /*TRI=*/nullptr);
913     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
917     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
1296   bool BaseKill = BaseOP.isKill();
1328       if (!STI->hasMinSize() || !BaseKill)
1352     .addReg(Base, getKillRegState(BaseKill))
1476   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
1533                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1737                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,
1744       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1753       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1796   bool BaseKill = BaseOp.isKill();
1812         .addReg(BaseReg, getKillRegState(BaseKill))
1820         .addReg(BaseReg, getKillRegState(BaseKill))
1846                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1863                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,