Lines Matching +full:asi +full:- +full:format
1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 // ARM Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>;
22 def MulFrm : Format<1>;
23 def BrFrm : Format<2>;
24 def BrMiscFrm : Format<3>;
26 def DPFrm : Format<4>;
27 def DPSoRegRegFrm : Format<5>;
29 def LdFrm : Format<6>;
30 def StFrm : Format<7>;
31 def LdMiscFrm : Format<8>;
32 def StMiscFrm : Format<9>;
33 def LdStMulFrm : Format<10>;
35 def LdStExFrm : Format<11>;
37 def ArithMiscFrm : Format<12>;
38 def SatFrm : Format<13>;
39 def ExtFrm : Format<14>;
41 def VFPUnaryFrm : Format<15>;
42 def VFPBinaryFrm : Format<16>;
43 def VFPConv1Frm : Format<17>;
44 def VFPConv2Frm : Format<18>;
45 def VFPConv3Frm : Format<19>;
46 def VFPConv4Frm : Format<20>;
47 def VFPConv5Frm : Format<21>;
48 def VFPLdStFrm : Format<22>;
49 def VFPLdStMulFrm : Format<23>;
50 def VFPMiscFrm : Format<24>;
52 def ThumbFrm : Format<25>;
53 def MiscFrm : Format<26>;
55 def NGetLnFrm : Format<27>;
56 def NSetLnFrm : Format<28>;
57 def NDupFrm : Format<29>;
58 def NLdStFrm : Format<30>;
59 def N1RegModImmFrm: Format<31>;
60 def N2RegFrm : Format<32>;
61 def NVCVTFrm : Format<33>;
62 def NVDupLnFrm : Format<34>;
63 def N2RegVShLFrm : Format<35>;
64 def N2RegVShRFrm : Format<36>;
65 def N3RegFrm : Format<37>;
66 def N3RegVShFrm : Format<38>;
67 def NVExtFrm : Format<39>;
68 def NVMulSLFrm : Format<40>;
69 def NVTBLFrm : Format<41>;
70 def DPSoRegImmFrm : Format<42>;
71 def N3RegCplxFrm : Format<43>;
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
84 //===----------------------------------------------------------------------===//
88 // FIXME: Once the JIT is MC-ized, these can go away.
138 //===----------------------------------------------------------------------===//
172 // all other respects it is identical though: pseudo-instruction expansion
203 ARMCC::CondCodes CC = static_cast<ARMCC::CondCodes>(N->getZExtValue());
204 return CurDAG->getTargetConstant(ARMCC::getOppositeCondition(CC), SDLoc(N),
224 // VPT-predicated MVE instruction.
239 // explicit operand so that it can be register-allocated and spilled
273 // vpred_r it ties the $inactive operand to the output q-register
323 // Shift Right Immediate - A shift right immediate is encoded differently from
327 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
328 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
329 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
330 // 64 64 - <imm> is encoded in imm6<5:0>
365 //===----------------------------------------------------------------------===//
401 //===----------------------------------------------------------------------===//
407 Format f, Domain d, string cstr, InstrItinClass itin>
415 Format F = f;
420 // The instruction is a 16-bit flag setting Thumb instruction. Used
421 // by the parser and if-converter to determine whether to require the 'S'
436 let TSFlags{4-0} = AM.Value;
437 let TSFlags{6-5} = IndexModeBits;
438 let TSFlags{12-7} = Form;
441 let TSFlags{18-15} = D.Value;
447 let TSFlags{25-24} = VecSize;
461 // as to make it more obvious what it means in ARM-land.
466 Format f, Domain d, string cstr, InstrItinClass itin>
471 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
474 Format f, Domain d, string cstr, InstrItinClass itin>
479 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
518 // PseudoInst that's ARM-mode only.
526 // PseudoInst that's Thumb-mode only.
534 // PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2)
542 // PseudoInst that's Thumb2-mode only.
570 IndexMode im, Format f, InstrItinClass itin,
575 let Inst{31-28} = p;
585 IndexMode im, Format f, InstrItinClass itin,
601 IndexMode im, Format f, InstrItinClass itin,
606 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
607 let Inst{31-28} = p;
619 IndexMode im, Format f, InstrItinClass itin,
629 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
633 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
637 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
641 class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
645 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
655 let Inst{27-24} = opcod;
661 let Inst{27-24} = opcod;
676 let Inst{27-23} = 0b00011;
677 let Inst{22-21} = opcod;
679 let Inst{19-16} = addr;
680 let Inst{15-12} = Rt;
681 let Inst{11-10} = 0b11;
682 let Inst{9-8} = opcod2;
683 let Inst{7-0} = 0b10011111;
691 let Inst{27-23} = 0b00011;
692 let Inst{22-21} = opcod;
694 let Inst{19-16} = addr;
695 let Inst{11-10} = 0b11;
696 let Inst{9-8} = opcod2;
697 let Inst{7-4} = 0b1001;
698 let Inst{3-0} = Rt;
709 let Inst{15-12} = Rd;
724 let Inst{15-12} = Rd;
732 let Inst{27-23} = 0b00010;
734 let Inst{21-20} = 0b00;
735 let Inst{19-16} = addr;
736 let Inst{15-12} = Rt;
737 let Inst{11-4} = 0b00001001;
738 let Inst{3-0} = Rt2;
740 let Unpredictable{11-8} = 0b1111;
753 let Inst{15-12} = 0b1111;
757 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
761 let Inst{24-21} = opcod;
762 let Inst{27-26} = 0b00;
764 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
768 let Inst{24-21} = opcod;
769 let Inst{27-26} = 0b00;
771 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
775 let Inst{24-21} = opcod;
776 let Inst{27-26} = 0b00;
783 Format f, InstrItinClass itin, string opc, string asm,
787 let Inst{27-25} = op;
796 IndexMode im, Format f, InstrItinClass itin, string opc,
801 let Inst{27-26} = 0b01;
806 let Inst{15-12} = Rt;
809 IndexMode im, Format f, InstrItinClass itin, string opc,
815 // {11-0} imm12/Rm
820 let Inst{19-16} = Rn;
821 let Inst{11-5} = offset{11-5};
823 let Inst{3-0} = offset{3-0};
827 IndexMode im, Format f, InstrItinClass itin, string opc,
833 // {11-0} imm12/Rm
838 let Inst{19-16} = Rn;
839 let Inst{11-0} = offset{11-0};
846 IndexMode im, Format f, InstrItinClass itin, string opc,
851 // {17-14} Rn
854 // {11-0} imm12/Rm
858 let Inst{19-16} = addr{17-14};
859 let Inst{11-0} = addr{11-0};
863 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
869 let Inst{27-25} = 0b000;
875 let Inst{19-16} = addr{12-9}; // Rn
876 let Inst{15-12} = Rt; // Rt
877 let Inst{11-8} = addr{7-4}; // imm7_4/zero
878 let Inst{7-4} = op;
879 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
885 IndexMode im, Format f, InstrItinClass itin, string opc,
890 let Inst{27-25} = 0b000;
894 let Inst{15-12} = Rt; // Rt
895 let Inst{7-4} = op;
901 IndexMode im, Format f, InstrItinClass itin, string opc,
905 // {12-9} Rn
907 // {7-4} imm7_4/zero
908 // {3-0} imm3_0/Rm
911 let Inst{27-25} = 0b000;
915 let Inst{19-16} = addr; // Rn
916 let Inst{15-12} = Rt; // Rt
917 let Inst{7-4} = op;
921 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
927 let Inst{27-25} = 0b000;
933 let Inst{19-16} = addr{12-9}; // Rn
934 let Inst{15-12} = Rt; // Rt
935 let Inst{11-8} = addr{7-4}; // imm7_4/zero
936 let Inst{7-4} = op;
937 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
942 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
948 let Inst{31-28} = p;
949 let Inst{27-25} = 0b100;
951 let Inst{19-16} = Rn;
952 let Inst{15-0} = regs;
955 // Unsigned multiply, multiply-accumulate instructions.
960 let Inst{7-4} = 0b1001;
962 let Inst{27-21} = opcod;
968 let Inst{7-4} = 0b1001;
969 let Inst{27-21} = opcod;
980 let Inst{7-4} = opc7_4;
982 let Inst{27-21} = opcod;
983 let Inst{19-16} = Rd;
984 let Inst{11-8} = Rm;
985 let Inst{3-0} = Rn;
992 let Inst{15-12} = Ra;
1005 let Inst{27-21} = opcod;
1006 let Inst{6-5} = bit6_5;
1007 let Inst{11-8} = Rm;
1008 let Inst{3-0} = Rn;
1014 let Inst{19-16} = Rd;
1022 let Inst{15-12} = Ra;
1030 let Inst{19-16} = RdHi;
1031 let Inst{15-12} = RdLo;
1042 let Inst{15-12} = Rd;
1043 let Inst{3-0} = Rm;
1044 let Inst{7-4} = 0b0111;
1045 let Inst{9-8} = 0b00;
1046 let Inst{27-20} = opcod;
1048 let Unpredictable{9-8} = 0b11;
1058 let Inst{27-20} = opcod;
1059 let Inst{19-16} = 0b1111;
1060 let Inst{15-12} = Rd;
1061 let Inst{11-8} = 0b1111;
1062 let Inst{7-4} = opc7_4;
1063 let Inst{3-0} = Rm;
1074 let Inst{27-23} = 0b01110;
1075 let Inst{22-20} = opcod;
1076 let Inst{19-16} = Rd;
1077 let Inst{15-12} = 0b1111;
1078 let Inst{11-8} = Rm;
1079 let Inst{7-4} = 0b0001;
1080 let Inst{3-0} = Rn;
1109 let Inst{27-20} = opcod;
1110 let Inst{19-16} = Rn;
1111 let Inst{15-12} = Rd;
1112 let Inst{11-7} = sh;
1114 let Inst{5-4} = 0b01;
1115 let Inst{3-0} = Rm;
1118 //===----------------------------------------------------------------------===//
1120 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
1130 // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps.
1158 //===----------------------------------------------------------------------===//
1159 // Thumb Instruction Format Definitions.
1172 // TI - Thumb instruction.
1176 // Two-address instructions
1182 // tBL, tBX 32-bit instructions
1188 let Inst{31-27} = opcod1;
1189 let Inst{15-14} = opcod2;
1216 // Two-address instructions
1240 // Two-address instructions
1262 // Two-address instructions
1273 let Inst{31-16} = 0x0000;
1276 // A6.2 16-bit Thumb instruction encoding
1278 let Inst{15-10} = opcode;
1283 let Inst{15-14} = 0b00;
1284 let Inst{13-9} = opcode;
1287 // A6.2.2 Data-processing encoding.
1289 let Inst{15-10} = 0b010000;
1290 let Inst{9-6} = opcode;
1295 let Inst{15-10} = 0b010001;
1296 let Inst{9-6} = opcode;
1301 let Inst{15-12} = opA;
1302 let Inst{11-9} = opB;
1307 let Inst{15-12} = opcode;
1323 let Inst{8-6} = addr{5-3}; // Rm
1324 let Inst{5-3} = addr{2-0}; // Rn
1325 let Inst{2-0} = Rt;
1334 let Inst{10-6} = addr{7-3}; // imm5
1335 let Inst{5-3} = addr{2-0}; // Rn
1336 let Inst{2-0} = Rt;
1339 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1341 let Inst{15-12} = 0b1011;
1342 let Inst{11-5} = opcode;
1345 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1368 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1429 let Inst{31-25} = 0b1110100;
1435 let Inst{19-16} = addr{12-9};
1436 let Inst{15-12} = Rt{3-0};
1437 let Inst{11-8} = Rt2{3-0};
1438 let Inst{7-0} = addr{7-0};
1449 let Inst{31-25} = 0b1110100;
1455 let Inst{19-16} = addr;
1456 let Inst{15-12} = Rt{3-0};
1457 let Inst{11-8} = Rt2{3-0};
1458 let Inst{7-0} = imm{7-0};
1476 let Inst{31-28} = opc;
1479 // Two-address instructions
1484 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1499 let Inst{31-27} = 0b11111;
1500 let Inst{26-25} = 0b00;
1503 let Inst{22-21} = opcod;
1505 let Inst{19-16} = addr{12-9};
1506 let Inst{15-12} = Rt{3-0};
1508 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1512 let Inst{7-0} = addr{7-0};
1517 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1533 let Inst{31-27} = 0b11111;
1534 let Inst{26-25} = 0b00;
1537 let Inst{22-21} = opcod;
1539 let Inst{19-16} = Rn;
1540 let Inst{15-12} = Rt{3-0};
1542 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1546 let Inst{7-0} = offset{7-0};
1551 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1556 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1561 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1566 //===----------------------------------------------------------------------===//
1568 //===----------------------------------------------------------------------===//
1574 IndexMode im, Format f, InstrItinClass itin,
1578 let Inst{31-28} = p;
1590 IndexMode im, Format f, InstrItinClass itin,
1594 let Inst{31-28} = p;
1604 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1624 let Inst{19-16} = addr{12-9}; // Rn
1625 let Inst{15-12} = Dd{3-0};
1626 let Inst{7-0} = addr{7-0}; // imm8
1628 let Inst{27-24} = opcod1;
1629 let Inst{21-20} = opcod2;
1630 let Inst{11-9} = 0b101;
1649 let Inst{19-16} = addr{12-9}; // Rn
1650 let Inst{15-12} = Sd{4-1};
1651 let Inst{7-0} = addr{7-0}; // imm8
1653 let Inst{27-24} = opcod1;
1654 let Inst{21-20} = opcod2;
1655 let Inst{11-9} = 0b101;
1676 let Inst{19-16} = addr{12-9}; // Rn
1677 let Inst{15-12} = Sd{4-1};
1678 let Inst{7-0} = addr{7-0}; // imm8
1680 let Inst{27-24} = opcod1;
1681 let Inst{21-20} = opcod2;
1682 let Inst{11-8} = 0b1001; // Half precision
1713 let Inst{19-16} = Rn;
1715 let Inst{15-12} = regs{11-8};
1716 let Inst{7-1} = regs{7-1};
1718 let Inst{27-25} = 0b110;
1719 let Inst{11-8} = 0b1011;
1733 let Inst{19-16} = Rn;
1735 let Inst{15-12} = regs{11-8};
1736 let Inst{7-1} = regs{7-1};
1738 let Inst{27-25} = 0b110;
1739 let Inst{11-9} = 0b101;
1754 let Inst{19-16} = Rn;
1756 let Inst{15-12} = regs{12-9};
1757 let Inst{7-0} = regs{7-0};
1759 let Inst{27-25} = 0b110;
1760 let Inst{11-9} = 0b101;
1765 // For when the registers-to-be-stored/loaded are fixed, e.g. VLLDM and VLSTM
1778 let Inst{19-16} = Rn;
1779 let Inst{31-28} = 0b1110;
1780 let Inst{27-25} = 0b110;
1786 let Inst{15-12} = 0b0000;
1787 let Inst{11-9} = 0b101;
1790 let Inst{6-0} = 0b0000000;
1805 let Inst{3-0} = Dm{3-0};
1807 let Inst{15-12} = Dd{3-0};
1810 let Inst{27-23} = opcod1;
1811 let Inst{21-20} = opcod2;
1812 let Inst{19-16} = opcod3;
1813 let Inst{11-9} = 0b101;
1815 let Inst{7-6} = opcod4;
1821 // Double precision, unary, not-predicated
1830 let Inst{31-28} = 0b1111;
1833 let Inst{3-0} = Dm{3-0};
1835 let Inst{15-12} = Dd{3-0};
1838 let Inst{27-23} = opcod1;
1839 let Inst{21-20} = opcod2;
1840 let Inst{19-16} = opcod3;
1841 let Inst{11-9} = 0b101;
1843 let Inst{7-6} = opcod4;
1858 let Inst{3-0} = Dm{3-0};
1860 let Inst{19-16} = Dn{3-0};
1862 let Inst{15-12} = Dd{3-0};
1865 let Inst{27-23} = opcod1;
1866 let Inst{21-20} = opcod2;
1867 let Inst{11-9} = 0b101;
1886 let Inst{31-28} = 0b1111;
1889 let Inst{3-0} = Dm{3-0};
1891 let Inst{19-16} = Dn{3-0};
1893 let Inst{15-12} = Dd{3-0};
1896 let Inst{27-23} = opcod1;
1897 let Inst{21-20} = opcod2;
1898 let Inst{11-9} = 0b101;
1916 let Inst{3-0} = Sm{4-1};
1918 let Inst{15-12} = Sd{4-1};
1921 let Inst{27-23} = opcod1;
1922 let Inst{21-20} = opcod2;
1923 let Inst{19-16} = opcod3;
1924 let Inst{11-9} = 0b101;
1926 let Inst{7-6} = opcod4;
1930 // Single precision, unary, non-predicated
1940 let Inst{31-28} = 0b1111;
1943 let Inst{3-0} = Sm{4-1};
1945 let Inst{15-12} = Sd{4-1};
1948 let Inst{27-23} = opcod1;
1949 let Inst{21-20} = opcod2;
1950 let Inst{19-16} = opcod3;
1951 let Inst{11-9} = 0b101;
1953 let Inst{7-6} = opcod4;
1977 let Inst{3-0} = Sm{4-1};
1979 let Inst{19-16} = Sn{4-1};
1981 let Inst{15-12} = Sd{4-1};
1984 let Inst{27-23} = opcod1;
1985 let Inst{21-20} = opcod2;
1986 let Inst{11-9} = 0b101;
2003 let Inst{31-28} = 0b1111;
2006 let Inst{3-0} = Sm{4-1};
2008 let Inst{19-16} = Sn{4-1};
2010 let Inst{15-12} = Sd{4-1};
2013 let Inst{27-23} = opcod1;
2014 let Inst{21-20} = opcod2;
2015 let Inst{11-9} = 0b101;
2035 let Inst{3-0} = Sm{4-1};
2037 let Inst{19-16} = Sn{4-1};
2039 let Inst{15-12} = Sd{4-1};
2055 let Inst{3-0} = Sm{4-1};
2057 let Inst{15-12} = Sd{4-1};
2060 let Inst{27-23} = opcod1;
2061 let Inst{21-20} = opcod2;
2062 let Inst{19-16} = opcod3;
2063 let Inst{11-8} = 0b1001; // Half precision
2064 let Inst{7-6} = opcod4;
2070 // Half precision, unary, non-predicated
2082 let Inst{31-28} = 0b1111;
2085 let Inst{3-0} = Sm{4-1};
2087 let Inst{15-12} = Sd{4-1};
2090 let Inst{27-23} = opcod1;
2091 let Inst{21-20} = opcod2;
2092 let Inst{19-16} = opcod3;
2093 let Inst{11-8} = 0b1001; // Half precision
2094 let Inst{7-6} = opcod4;
2112 let Inst{3-0} = Sm{4-1};
2114 let Inst{19-16} = Sn{4-1};
2116 let Inst{15-12} = Sd{4-1};
2119 let Inst{27-23} = opcod1;
2120 let Inst{21-20} = opcod2;
2121 let Inst{11-8} = 0b1001; // Half precision
2140 let Inst{31-28} = 0b1111;
2143 let Inst{3-0} = Sm{4-1};
2145 let Inst{19-16} = Sn{4-1};
2147 let Inst{15-12} = Sd{4-1};
2150 let Inst{27-23} = opcod1;
2151 let Inst{21-20} = opcod2;
2152 let Inst{11-8} = 0b1001; // Half precision
2164 let Inst{27-23} = opcod1;
2165 let Inst{21-20} = opcod2;
2166 let Inst{19-16} = opcod3;
2167 let Inst{11-8} = opcod4;
2172 // VFP conversion between floating-point and fixed-point
2178 // size (fixed-point number): sx == 0 ? 16 : 32
2181 let Inst{3-0} = fbits{4-1};
2193 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
2197 let Inst{27-20} = opcod1;
2198 let Inst{11-8} = opcod2;
2218 //===----------------------------------------------------------------------===//
2220 //===----------------------------------------------------------------------===//
2224 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2237 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2250 class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2261 let Inst{31-28} = 0b1111;
2269 let Inst{31-24} = 0b11110100;
2271 let Inst{21-20} = op21_20;
2272 let Inst{11-8} = op11_8;
2273 let Inst{7-4} = op7_4;
2283 let Inst{15-12} = Vd{3-0};
2284 let Inst{19-16} = Rn{3-0};
2285 let Inst{3-0} = Rm{3-0};
2314 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
2318 let Inst{31-25} = 0b1111001;
2323 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
2327 let Inst{31-25} = 0b1111001;
2332 // NEON "one register and a modified immediate" format.
2340 let Inst{21-19} = op21_19;
2341 let Inst{11-8} = op11_8;
2351 let Inst{15-12} = Vd{3-0};
2354 let Inst{18-16} = SIMM{6-4};
2355 let Inst{3-0} = SIMM{3-0};
2359 // NEON 2 vector register format.
2365 let Inst{24-23} = op24_23;
2366 let Inst{21-20} = op21_20;
2367 let Inst{19-18} = op19_18;
2368 let Inst{17-16} = op17_16;
2369 let Inst{11-7} = op11_7;
2377 let Inst{15-12} = Vd{3-0};
2379 let Inst{3-0} = Vm{3-0};
2394 let Inst{15-12} = Vd{3-0};
2396 let Inst{3-0} = Vm{3-0};
2399 let Inst{27-23} = 0b00111;
2400 let Inst{21-20} = 0b11;
2401 let Inst{19-18} = op19_18;
2402 let Inst{17-16} = op17_16;
2404 let Inst{10-8} = op10_8;
2418 let Inst{24-23} = op24_23;
2419 let Inst{21-20} = op21_20;
2420 let Inst{19-18} = op19_18;
2421 let Inst{17-16} = op17_16;
2422 let Inst{11-7} = op11_7;
2430 let Inst{15-12} = Vd{3-0};
2432 let Inst{3-0} = Vm{3-0};
2438 dag oops, dag iops, Format f, InstrItinClass itin,
2443 let Inst{11-8} = op11_8;
2453 let Inst{15-12} = Vd{3-0};
2455 let Inst{3-0} = Vm{3-0};
2457 let Inst{21-16} = SIMM{5-0};
2460 // NEON 3 vector register format.
2463 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2469 let Inst{21-20} = op21_20;
2470 let Inst{11-8} = op11_8;
2476 dag oops, dag iops, Format f, InstrItinClass itin,
2485 let Inst{15-12} = Vd{3-0};
2487 let Inst{19-16} = Vn{3-0};
2489 let Inst{3-0} = Vm{3-0};
2494 bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
2504 let Inst{15-12} = Vd{3-0};
2505 let Inst{19-16} = Vn{3-0};
2508 let Inst{3-0} = Vm{3-0};
2511 let Inst{27-23} = op27_23;
2512 let Inst{21-20} = op21_20;
2513 let Inst{11-8} = op11_8;
2519 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2531 let Inst{15-12} = Vd{3-0};
2533 let Inst{19-16} = Vn{3-0};
2535 let Inst{3-0} = Vm{3-0};
2540 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2552 let Inst{15-12} = Vd{3-0};
2554 let Inst{19-16} = Vn{3-0};
2556 let Inst{2-0} = Vm{2-0};
2564 dag oops, dag iops, Format f, InstrItinClass itin,
2569 let Inst{21-20} = op21_20;
2570 let Inst{11-8} = op11_8;
2579 let Inst{15-12} = Vd{3-0};
2581 let Inst{19-16} = Vn{3-0};
2583 let Inst{3-0} = Vm{3-0};
2589 dag oops, dag iops, Format f, InstrItinClass itin,
2593 let Inst{27-20} = opcod1;
2594 let Inst{11-8} = opcod2;
2595 let Inst{6-5} = opcod3;
2598 let Inst{3-0} = 0b0000;
2614 let Inst{31-28} = p{3-0};
2616 let Inst{19-16} = V{3-0};
2617 let Inst{15-12} = R{3-0};
2640 let Inst{24-23} = 0b11;
2641 let Inst{21-20} = 0b11;
2642 let Inst{19-16} = op19_16;
2643 let Inst{11-7} = 0b11000;
2651 let Inst{15-12} = Vd{3-0};
2653 let Inst{3-0} = Vm{3-0};
2656 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2657 // for single-precision FP.
2693 // Extension of NEON 3-vector data processing instructions in coprocessor 8
2694 // encoding space, introduced in ARMv8.3-A.
2708 let Inst{31-25} = 0b1111110;
2709 let Inst{24-23} = op24_23;
2711 let Inst{21-20} = op21_20;
2712 let Inst{19-16} = Vn{3-0};
2713 let Inst{15-12} = Vd{3-0};
2714 let Inst{11-8} = 0b1000;
2719 let Inst{3-0} = Vm{3-0};
2722 // Extension of NEON 2-vector-and-scalar data processing instructions in
2723 // coprocessor 8 encoding space, introduced in ARMv8.3-A.
2737 let Inst{31-24} = 0b11111110;
2740 let Inst{21-20} = op21_20;
2741 let Inst{19-16} = Vn{3-0};
2742 let Inst{15-12} = Vd{3-0};
2743 let Inst{11-8} = 0b1000;
2746 // Bit 5 set by sub-classes
2748 let Inst{3-0} = Vm{3-0};
2751 // In Armv8.2-A, some NEON instructions are added that encode Vn and Vm
2768 let Inst{31-25} = 0b1111110;
2769 let Inst{24-23} = op24_23;
2771 let Inst{21-20} = op21_20;
2772 let Inst{19-16} = Vn{4-1};
2773 let Inst{15-12} = Vd{3-0};
2774 let Inst{11-8} = 0b1000;
2779 let Inst{3-0} = Vm{4-1};
2808 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.