Lines Matching defs:isSEXTLoad

9470   if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
9563     assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) &&
9568     unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
19786                                       bool isSEXTLoad, SDValue &Base,
19792   if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
19845                                      bool isSEXTLoad, SDValue &Base,
19870                                       bool isSEXTLoad, bool IsMasked, bool isLE,
19936   bool isSEXTLoad = false;
19942     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19951     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
19966                   Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked,
19970       isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
19973       isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
19994   bool isSEXTLoad = false, isNonExt;
20000     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
20011     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
20045               getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked,
20050       isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
20053       isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,