Lines Matching defs:VMOVRRD
1411 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1598 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1742 MAKE_CASE(ARMISD::VMOVRRD)
2335 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3292 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3314 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3383 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
5256 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
5258 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
6095 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
6111 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
6246 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
6286 // Turn f64->i64 into VMOVRRD.
6291 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
6295 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
15052 /// ARMISD::VMOVRRD.
15092 // VMOVRRD(extract(..(build_vector(a, b, c, d)))) -> a,b or c,d
15093 // VMOVRRD(extract(insert_vector(insert_vector(.., a, l1), b, l2))) -> a,b
15153 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
15273 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
15274 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
15276 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
15508 // Convert a pair of extracts from the same base vector to a VMOVRRD. Either
15510 // extract(x, n); extract(x, n+1) -> VMOVRRD(extract v2f64 x, n/2)
15511 // bitcast(extract(x, n)); bitcast(extract(x, n+1)) -> VMOVRRD(extract x, n/2)
15562 // Convert the type to a f64 and extract with a VMOVRRD.
15567 SDValue VMOVRRD =
15568 DCI.DAG.getNode(ARMISD::VMOVRRD, dl, {MVT::i32, MVT::i32}, F64);
15570 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1));
15571 return VMOVRRD;
15617 // extract x, n; extract x, n+1 -> VMOVRRD x
18598 // bitcast(extract(x, n)); bitcast(extract(x, n+1)) -> VMOVRRD x
18902 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);