Lines Matching defs:SRL
206 setOperationAction(ISD::SRL, VT, Custom);
269 setOperationAction(ISD::SRL, VT, Custom);
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1178 setOperationAction(ISD::SRL, MVT::i64, Custom);
1186 // assuming that ISD::SRL and SRA of i64 are already marked custom
1606 setTargetDAGCombine(ISD::SRL);
2006 if (Op.getOpcode() != ISD::SRL)
6332 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
6338 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
6380 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
6418 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
6683 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6712 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6732 if (ShOpc == ISD::SRL) {
6756 // We only lower SRA, SRL of 1 here, all others use generic lowering.
6764 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
6770 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_GLUE:ARMISD::SRA_GLUE;
8639 SDValue srl = DAG.getNode(ISD::SRL, dl, MVT::i32, rbit,
8963 Lo = DAG.getNode(ISD::SRL, dl, FromVT, Lo, Amt);
8964 Hi = DAG.getNode(ISD::SRL, dl, FromVT, Hi, Amt);
9117 SDValue Shift = DAG.getNode(ISD::SRL, dl, MVT::i32, Conv,
10121 SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
10156 Val = DAG.getNode(ISD::SRL, dl, MVT::i32,
10215 GRP = DAG.getNode(ISD::SRL, dl, MVT::i32,
10603 case ISD::SRL:
10738 case ISD::SRL:
13803 N->getOpcode() == ISD::SRL) &&
13843 N->getOperand(0).getOpcode() == ISD::SRL) &&
13866 N->getOperand(0).getOpcode() == ISD::SRL) ||
13867 (N->getOpcode() == ISD::SRL &&
14323 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
14356 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14365 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14380 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14391 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14470 SDValue SRL = OR->getOperand(0);
14473 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
14474 SRL = OR->getOperand(1);
14477 if (!isSRL16(SRL) || !isSHL16(SHL))
14482 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
14483 SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)
14486 SDNode *SMULLOHI = SRL.getOperand(0).getNode();
14487 if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
14597 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
14614 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
14859 if (From->getOpcode() == ISD::SRL &&
14953 From1 = DAG.getNode(ISD::SRL, dl, VT, From1,
17755 ISD::SRL, DL, MVT::i32, SHL,
17782 case ISD::SRL:
18159 X = DAG.getNode(ISD::SRL, dl, VT, X,
18467 // CMOV 0, 1, ==, (CMPZ x, y) -> SRL (CTLZ (SUB x, y)), 5
18469 Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub),
18927 case ISD::SRL:
20868 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,