Lines Matching defs:SRA
205 setOperationAction(ISD::SRA, VT, Custom);
268 setOperationAction(ISD::SRA, VT, Custom);
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1179 setOperationAction(ISD::SRA, MVT::i64, Custom);
1186 // assuming that ISD::SRL and SRA of i64 are already marked custom
2014 if (Op.getOpcode() != ISD::SRA)
2029 // Check for a signed 16-bit value. We special case SRA because it makes it
4136 SDValue SRA =
4137 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
4138 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
4156 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
4985 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
5447 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
6332 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
6350 SDValue HiBigShift = Opc == ISD::SRA
6683 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
6688 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
6699 (N->getOpcode() == ISD::SRA ? ARMISD::VSHLs : ARMISD::VSHLu);
6712 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA ||
6741 } else if (ShOpc == ISD::SRA)
6756 // We only lower SRA, SRL of 1 here, all others use generic lowering.
6764 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
10604 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
10739 case ISD::SRA:
12835 // be sign extended somehow or SRA'd into 32-bit values
12846 SDValue SRA = AddeNode->getOperand(0);
12848 if (SRA.getOpcode() != ISD::SRA) {
12849 SRA = AddeNode->getOperand(1);
12851 if (SRA.getOpcode() != ISD::SRA)
12854 if (auto Const = dyn_cast<ConstantSDNode>(SRA.getOperand(1))) {
12860 if (SRA.getOperand(0) != Mul)
13365 if (Shft.getOpcode() != ISD::SRA)
13802 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
14495 // For SMULWT only the SRA is required.
17781 case ISD::SRA:
17785 (N->getOpcode() == ISD::SRA ? ARMISD::VSHRsIMM : ARMISD::VSHRuIMM);
18926 case ISD::SRA: