Lines Matching defs:SHL
204 setOperationAction(ISD::SHL, VT, Custom);
267 setOperationAction(ISD::SHL, VT, Custom);
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1188 setOperationAction(ISD::SHL, MVT::i64, Custom);
1608 setTargetDAGCombine(ISD::SHL);
2022 if (Op.getOpcode() != ISD::SHL)
3660 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
4139 SDValue SHL =
4140 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4142 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4158 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4826 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4838 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
6341 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
6381 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
6386 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
6394 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6446 RMValue = DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
6675 if (N->getOpcode() == ISD::SHL) {
6708 // We can get here for a node like i32 = ISD::SHL i32, i64
6713 N->getOpcode() == ISD::SHL) &&
6757 if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL)
10602 case ISD::SHL:
10740 case ISD::SHL:
13802 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
13809 if (N->getOpcode() != ISD::SHL)
13816 if (N->getOpcode() != ISD::SHL)
13842 (N->getOperand(0).getOpcode() == ISD::SHL ||
13854 if (N->getOperand(0).getOpcode() == ISD::SHL)
13865 assert(((N->getOpcode() == ISD::SHL &&
13868 N->getOperand(0).getOpcode() == ISD::SHL)) &&
13960 if (U->getOperand(0).getOpcode() == ISD::SHL ||
13961 U->getOperand(1).getOpcode() == ISD::SHL)
13971 if (N->getOperand(0).getOpcode() != ISD::SHL)
13974 SDValue SHL = N->getOperand(0);
13977 auto *C2 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
14007 SDValue X = SHL.getOperand(0);
14011 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1));
14013 LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump();
14014 SHL.dump(); N->dump());
14253 DAG.getNode(ISD::SHL, DL, VT,
14260 DAG.getNode(ISD::SHL, DL, VT,
14273 DAG.getNode(ISD::SHL, DL, VT,
14281 DAG.getNode(ISD::SHL, DL, VT,
14292 Res = DAG.getNode(ISD::SHL, DL, VT,
14323 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
14326 bool LeftShift = N0->getOpcode() == ISD::SHL;
14354 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14356 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14365 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14367 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
14378 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14380 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14391 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14393 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
14405 return DAG.getNode(ISD::SHL, DL, MVT::i32, And,
14471 SDValue SHL = OR->getOperand(1);
14473 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
14475 SHL = OR->getOperand(0);
14477 if (!isSRL16(SRL) || !isSHL16(SHL))
14482 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
14488 SHL.getOperand(0) != SDValue(SMULLOHI, 1))
14626 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
17727 if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 &&
17752 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
17755 ISD::SRL, DL, MVT::i32, SHL,
17773 case ISD::SHL:
18525 // Result = if K != 0 then (SHL t2:0, K) else t2:0
18532 // Result = if K != 0 then (SHL t2:0, K) else t2:0
18548 Res = DAG.getNode(ISD::SHL, dl, VT, Res,
18925 case ISD::SHL:
19444 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
20296 ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1),