Lines Matching defs:N1
7709 SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0,
7711 return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1,
9608 SDNode *N1 = N->getOperand(1).getNode();
9609 return N0->hasOneUse() && N1->hasOneUse() &&
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
9619 SDNode *N1 = N->getOperand(1).getNode();
9620 return N0->hasOneUse() && N1->hasOneUse() &&
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
9633 SDNode *N1 = Op.getOperand(1).getNode();
9637 bool isN1SExt = isSignExtended(N1, DAG);
9642 bool isN1ZExt = isZeroExtended(N1, DAG);
9654 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
9655 std::swap(N0, N1);
9674 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
9732 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl,
9741 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
9743 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
9750 N1);
9751 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
9753 N1, N2);
9754 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
9761 N1 = DAG.getConstant(0x89, dl, MVT::v4i32);
9762 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
9779 SDValue N1 = Op.getOperand(1);
9784 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
9788 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9792 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9795 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
9804 return LowerSDIV_v4i16(N0, N1, dl, DAG);
9816 SDValue N1 = Op.getOperand(1);
9821 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
9825 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9829 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
9832 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
9849 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
9851 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
9860 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
9863 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
9864 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
9867 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
9874 N1 = DAG.getConstant(2, dl, MVT::v4i32);
9875 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
12526 SDValue N1 = N->getOperand(1);
12528 if (isZeroOrAllOnes(N1, AllOnes)) {
12535 OtherOp = N1;
12620 SDValue N1 = N->getOperand(1);
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
12624 if (N1.getNode()->hasOneUse())
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
12642 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1,
12646 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() ||
12647 N0 == N1)
12670 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1,
12675 N1.getOpcode() == ISD::SIGN_EXTEND) &&
12677 N1.getOpcode() == ISD::ZERO_EXTEND))
12681 SDValue N10 = N1.getOperand(0);
12723 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
12730 || N1.getOpcode() != ISD::BUILD_VECTOR)
12739 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
12756 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
12759 SDValue ExtVec1 = N1->getOperand(i);
13367 ConstantSDNode *N1 = isConstOrConstSplat(Shft.getOperand(1));
13368 if (!N1 || N1->getSExtValue() != ShftAmt)
13542 /// operands N0 and N1. This is a helper for PerformADDCombine that is
13545 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI))
13569 SDValue N1 = N->getOperand(1);
13584 auto DistrubuteAddAddVecReduce = [&](SDValue N0, SDValue N1) {
13588 if (VT == MVT::i32 && N1.getOpcode() == ISD::ADD && !IsVecReduce(N0) &&
13589 IsVecReduce(N1.getOperand(0)) && IsVecReduce(N1.getOperand(1)) &&
13590 !isa<ConstantSDNode>(N0) && N1->hasOneUse()) {
13591 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0, N1.getOperand(0));
13592 return DAG.getNode(ISD::ADD, dl, VT, Add0, N1.getOperand(1));
13597 N1.getOpcode() == ISD::ADD && N0->hasOneUse() && N1->hasOneUse()) {
13606 if (!IsVecReduce(N1.getOperand(N1RedOp)))
13608 if (!IsVecReduce(N1.getOperand(N1RedOp)))
13612 N1.getOperand(1 - N1RedOp));
13615 return DAG.getNode(ISD::ADD, dl, VT, Add1, N1.getOperand(N1RedOp));
13619 if (SDValue R = DistrubuteAddAddVecReduce(N0, N1))
13621 if (SDValue R = DistrubuteAddAddVecReduce(N1, N0))
13628 auto DistrubuteVecReduceLoad = [&](SDValue N0, SDValue N1, bool IsForward) {
13630 // another. Return negative if N0 loads data before N1, positive if N1 is
13632 auto IsKnownOrderedLoad = [&](SDValue N0, SDValue N1) {
13637 if (N1.getOpcode() == ISD::MUL)
13638 N1 = N1.getOperand(0);
13643 LoadSDNode *Load1 = dyn_cast<LoadSDNode>(N1);
13684 } else if (IsForward && IsVecReduce(N0) && IsVecReduce(N1) &&
13685 IsKnownOrderedLoad(N0.getOperand(0), N1.getOperand(0)) < 0) {
13690 return DAG.getNode(ISD::ADD, dl, VT, N1, N0);
13694 if (!IsVecReduce(N0) || !IsVecReduce(N1))
13697 if (IsKnownOrderedLoad(N1.getOperand(0), N0.getOperand(0)) >= 0)
13700 // Switch from add(add(X, N0), N1) to add(add(X, N1), N0)
13701 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, X, N1);
13704 if (SDValue R = DistrubuteVecReduceLoad(N0, N1, true))
13706 if (SDValue R = DistrubuteVecReduceLoad(N1, N0, false))
13721 SDValue N1 = N->getOperand(1);
13764 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1))
13766 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N0, N1))
13768 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0))
13770 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N1, N0))
13772 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1))
13774 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N0, N1))
13776 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0))
13778 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N1, N0))
13780 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N0, N1))
13782 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N0, N1))
13784 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N1, N0))
13786 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0))
13788 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1))
13790 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N0, N1))
13792 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0))
13794 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N1, N0))
13818 SDValue N1 = N->getOperand(0);
13819 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND &&
13820 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
13822 if (auto *Const = dyn_cast<ConstantSDNode>(N1->getOperand(1))) {
13825 if (N1->getOpcode() == ISD::ADD && Const->getAPIntValue().slt(0) &&
14026 SDValue N1 = N->getOperand(1);
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget))
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
14069 SDValue N1 = N->getOperand(1);
14072 if (N1.getNode()->hasOneUse())
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
14126 SDValue N1 = N->getOperand(1);
14130 Opcode = N1.getOpcode();
14134 std::swap(N0, N1);
14137 if (N0 == N1)
14145 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
14146 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
14156 SDValue N1 = N->getOperand(1);
14197 if (SDValue Op1 = IsSignExt(N1)) {
14204 if (SDValue Op1 = IsZeroExt(N1)) {
14531 SDValue N1 = N->getOperand(1);
14561 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
14579 } else if (N1.getOpcode() == ISD::AND) {
14581 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
14597 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
14616 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
14625 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
14636 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
14686 SDValue N1 = N->getOperand(1);
14695 if (!(IsFreelyInvertable(N0) || IsFreelyInvertable(N1)))
14699 SDValue NewN1 = DAG.getLogicalNOT(DL, N1, VT);
14750 SDValue N1 = N->getOperand(1);
14753 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
14768 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
14785 N1->getOperand(0));
14826 SDValue N1 = N->getOperand(1);
14828 if (TLI->isConstTrueVal(N1) &&
14912 SDValue N1 = N->getOperand(1);
14914 if (N1.getOpcode() == ISD::AND) {
14917 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
14930 N->getOperand(0), N1.getOperand(0), N->getOperand(2));