Lines Matching defs:N0
9607 SDNode *N0 = N->getOperand(0).getNode();
9609 return N0->hasOneUse() && N1->hasOneUse() &&
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
9618 SDNode *N0 = N->getOperand(0).getNode();
9620 return N0->hasOneUse() && N1->hasOneUse() &&
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
9632 SDNode *N0 = Op.getOperand(0).getNode();
9636 bool isN0SExt = isSignExtended(N0, DAG);
9641 bool isN0ZExt = isZeroExtended(N0, DAG);
9648 if (isN1SExt && isAddSubSExt(N0, DAG)) {
9651 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
9655 std::swap(N0, N1);
9676 Op0 = SkipExtensionForVMULL(N0, DAG);
9691 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
9692 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
9694 return DAG.getNode(N0->getOpcode(), DL, VT,
9732 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl,
9740 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
9742 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
9759 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
9760 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
9762 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
9763 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
9766 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
9767 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
9768 return N0;
9778 SDValue N0 = Op.getOperand(0);
9783 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
9786 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
9790 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
9795 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
9798 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
9799 N0 = LowerCONCAT_VECTORS(N0, DAG, ST);
9801 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
9802 return N0;
9804 return LowerSDIV_v4i16(N0, N1, dl, DAG);
9815 SDValue N0 = Op.getOperand(0);
9820 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
9823 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
9827 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
9832 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
9835 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
9836 N0 = LowerCONCAT_VECTORS(N0, DAG, ST);
9838 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
9841 N0);
9842 return N0;
9848 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
9850 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
9872 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
9873 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
9875 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
9876 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
9879 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
9880 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
9881 return N0;
12619 SDValue N0 = N->getOperand(0);
12621 if (N0.getNode()->hasOneUse())
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
12642 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1,
12646 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() ||
12647 N0 == N1)
12658 SDNode *Unzip = N0.getNode();
12670 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1,
12674 if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
12676 !(N0.getOpcode() == ISD::ZERO_EXTEND &&
12680 SDValue N00 = N0.getOperand(0);
12691 !N0.getValueType().is128BitVector())
12703 if (N0.getOpcode() == ISD::SIGN_EXTEND)
12723 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
12729 || N0.getOpcode() != ISD::BUILD_VECTOR
12739 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
12745 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12747 SDValue Vec = N0->getOperand(0)->getOperand(0);
12754 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
12755 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
12758 SDValue ExtVec0 = N0->getOperand(i);
13542 /// operands N0 and N1. This is a helper for PerformADDCombine that is
13545 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
13560 if (N0.getNode()->hasOneUse())
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI))
13568 SDValue N0 = N->getOperand(0);
13584 auto DistrubuteAddAddVecReduce = [&](SDValue N0, SDValue N1) {
13588 if (VT == MVT::i32 && N1.getOpcode() == ISD::ADD && !IsVecReduce(N0) &&
13590 !isa<ConstantSDNode>(N0) && N1->hasOneUse()) {
13591 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0, N1.getOperand(0));
13596 if (VT == MVT::i32 && N0.getOpcode() == ISD::ADD &&
13597 N1.getOpcode() == ISD::ADD && N0->hasOneUse() && N1->hasOneUse()) {
13599 if (!IsVecReduce(N0.getOperand(N0RedOp))) {
13601 if (!IsVecReduce(N0.getOperand(N0RedOp)))
13611 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0.getOperand(1 - N0RedOp),
13614 DAG.getNode(ISD::ADD, dl, VT, Add0, N0.getOperand(N0RedOp));
13619 if (SDValue R = DistrubuteAddAddVecReduce(N0, N1))
13621 if (SDValue R = DistrubuteAddAddVecReduce(N1, N0))
13628 auto DistrubuteVecReduceLoad = [&](SDValue N0, SDValue N1, bool IsForward) {
13630 // another. Return negative if N0 loads data before N1, positive if N1 is
13631 // before N0 and 0 otherwise if nothing is known.
13632 auto IsKnownOrderedLoad = [&](SDValue N0, SDValue N1) {
13635 if (N0.getOpcode() == ISD::MUL)
13636 N0 = N0.getOperand(0);
13642 LoadSDNode *Load0 = dyn_cast<LoadSDNode>(N0);
13664 if (N0.getOpcode() == ISD::ADD && N0->hasOneUse()) {
13665 if (IsVecReduce(N0.getOperand(0)) && IsVecReduce(N0.getOperand(1))) {
13666 int IsBefore = IsKnownOrderedLoad(N0.getOperand(0).getOperand(0),
13667 N0.getOperand(1).getOperand(0));
13669 X = N0.getOperand(0);
13670 N0 = N0.getOperand(1);
13672 X = N0.getOperand(1);
13673 N0 = N0.getOperand(0);
13676 } else if (IsVecReduce(N0.getOperand(0))) {
13677 X = N0.getOperand(1);
13678 N0 = N0.getOperand(0);
13679 } else if (IsVecReduce(N0.getOperand(1))) {
13680 X = N0.getOperand(0);
13681 N0 = N0.getOperand(1);
13684 } else if (IsForward && IsVecReduce(N0) && IsVecReduce(N1) &&
13685 IsKnownOrderedLoad(N0.getOperand(0), N1.getOperand(0)) < 0) {
13690 return DAG.getNode(ISD::ADD, dl, VT, N1, N0);
13694 if (!IsVecReduce(N0) || !IsVecReduce(N1))
13697 if (IsKnownOrderedLoad(N1.getOperand(0), N0.getOperand(0)) >= 0)
13700 // Switch from add(add(X, N0), N1) to add(add(X, N1), N0)
13702 return DAG.getNode(ISD::ADD, dl, VT, Add0, N0);
13704 if (SDValue R = DistrubuteVecReduceLoad(N0, N1, true))
13706 if (SDValue R = DistrubuteVecReduceLoad(N1, N0, false))
13720 SDValue N0 = N->getOperand(0);
13764 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1))
13766 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N0, N1))
13768 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0))
13770 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N1, N0))
13772 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1))
13774 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N0, N1))
13776 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0))
13778 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N1, N0))
13780 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N0, N1))
13782 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N0, N1))
13784 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N1, N0))
13786 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0))
13788 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1))
13790 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N0, N1))
13792 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0))
13794 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N1, N0))
14025 SDValue N0 = N->getOperand(0);
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget))
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
14068 SDValue N0 = N->getOperand(0);
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
14125 SDValue N0 = N->getOperand(0);
14127 unsigned Opcode = N0.getOpcode();
14134 std::swap(N0, N1);
14137 if (N0 == N1)
14142 SDValue N00 = N0->getOperand(0);
14143 SDValue N01 = N0->getOperand(1);
14155 SDValue N0 = N->getOperand(0);
14196 if (SDValue Op0 = IsSignExt(N0)) {
14203 if (SDValue Op0 = IsZeroExt(N0)) {
14319 SDNode *N0 = N->getOperand(0).getNode();
14320 if (!N0->hasOneUse())
14323 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
14326 bool LeftShift = N0->getOpcode() == ISD::SHL;
14328 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
14354 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14365 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14378 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14391 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14403 SDValue And = DAG.getNode(ISD::AND, DL, MVT::i32, N0->getOperand(0),
14530 SDValue N0 = N->getOperand(0);
14547 SDValue N00 = N0.getOperand(0);
14552 SDValue MaskOp = N0.getOperand(1);
14685 SDValue N0 = N->getOperand(0);
14695 if (!(IsFreelyInvertable(N0) || IsFreelyInvertable(N1)))
14698 SDValue NewN0 = DAG.getLogicalNOT(DL, N0, VT);
14749 SDValue N0 = N->getOperand(0);
14759 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
14767 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
14783 N0->getOperand(1),
14784 N0->getOperand(0),
14794 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
14825 SDValue N0 = N->getOperand(0);
14829 (N0->getOpcode() == ARMISD::VCMP || N0->getOpcode() == ARMISD::VCMPZ)) {
14830 if (CanInvertMVEVCMP(N0)) {
14831 SDLoc DL(N0);
14832 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N0));
14835 Ops.push_back(N0->getOperand(0));
14836 if (N0->getOpcode() == ARMISD::VCMP)
14837 Ops.push_back(N0->getOperand(1));
14839 return DAG.getNode(N0->getOpcode(), DL, N0->getValueType(0), Ops);
14911 SDValue N0 = N->getOperand(0);
14965 APInt ToMask2 = ~N0.getConstantOperandAPInt(2);
14967 if (!N0.hasOneUse() || (ToMask1 & ToMask2) != 0 ||
14973 SDValue BFI1 = DAG.getNode(ARMISD::BFI, dl, VT, N0.getOperand(0),
14975 return DAG.getNode(ARMISD::BFI, dl, VT, BFI1, N0.getOperand(1),
14976 N0.getOperand(2));
15224 SDValue N0 = N->getOperand(0);
15228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0)) {
15234 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
15235 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
15241 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
15246 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
15247 isa<ConstantSDNode>(N0->getOperand(1)))
15248 return DAG.getNode(ARMISD::VGETLANEu, SDLoc(N), VT, N0->getOperand(0),
15249 N0->getOperand(1));
17102 SDValue N0 = N->getOperand(0);
17106 if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD &&
17107 (N0.getValueType() == MVT::v4i32 || N0.getValueType() == MVT::v8i16 ||
17108 N0.getValueType() == MVT::v16i8)) {
17109 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0));
17110 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1));
17145 if (ResVT != RetTy || N0->getOpcode() != ExtendCode)
17147 SDValue A = N0->getOperand(0);
17154 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||
17155 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode()))
17157 Mask = N0->getOperand(0);
17158 SDValue Ext = N0->getOperand(1);
17178 SDValue Mul = N0;
17204 // N0 = select Mask, Mul, 0
17205 // vecreduce.add N0
17206 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||
17207 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode()))
17209 Mask = N0->getOperand(0);
17210 SDValue Mul = N0->getOperand(1);
17333 SDValue Op = N0;
17341 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, N0->getValueType(0), Mul);
17342 if (Op != N0)
17343 Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0),
17344 N0->getOperand(0), Ext, N0->getOperand(2));
17736 SDValue N0 = N->getOperand(0);
17741 ConstantSDNode *AndMaskNode = dyn_cast<ConstantSDNode>(N0->getOperand(1));
17752 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
17799 SDValue N0 = N->getOperand(0);
17800 if (N0.getOpcode() != ISD::LOAD)
17802 LoadSDNode *LD = cast<LoadSDNode>(N0.getNode());
17803 if (!LD->isSimple() || !N0.hasOneUse() || LD->isIndexed() ||
17881 SDValue N0 = N->getOperand(0);
17888 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
17889 SDValue Vec = N0.getOperand(0);
17890 SDValue Lane = N0.getOperand(1);
17892 EVT EltVT = N0.getValueType();
17977 SDValue N0 = N->getOperand(0);
18014 if (IsSignedSaturate(N, N0.getNode())) {
18030 N0->getOperand(0), DAG.getConstant(0, DL, MVT::i32));
18070 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0,
18711 SDValue N0 = N->getOperand(0);
18712 LoadSDNode *LD = dyn_cast<LoadSDNode>(N0.getNode());
18713 if (!LD || !LD->isSimple() || !N0.hasOneUse() || LD->isIndexed())