Lines Matching defs:DCI
12587 // @param DCI Context.
12592 TargetLowering::DAGCombinerInfo &DCI,
12594 SelectionDAG &DAG = DCI.DAG;
12618 TargetLowering::DAGCombinerInfo &DCI) {
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
12643 TargetLowering::DAGCombinerInfo &DCI,
12655 SelectionDAG &DAG = DCI.DAG;
12671 TargetLowering::DAGCombinerInfo &DCI,
12695 SelectionDAG &DAG = DCI.DAG;
12724 TargetLowering::DAGCombinerInfo &DCI,
12728 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
12789 SelectionDAG &DAG = DCI.DAG;
12828 TargetLowering::DAGCombinerInfo &DCI,
12863 SelectionDAG &DAG = DCI.DAG;
12905 TargetLowering::DAGCombinerInfo &DCI,
12961 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget);
13021 SelectionDAG &DAG = DCI.DAG;
13071 TargetLowering::DAGCombinerInfo &DCI,
13080 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
13097 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
13109 SelectionDAG &DAG = DCI.DAG;
13148 TargetLowering::DAGCombinerInfo &DCI,
13150 SelectionDAG &DAG(DCI.DAG);
13159 return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
13181 TargetLowering::DAGCombinerInfo &DCI,
13184 SelectionDAG &DAG = DCI.DAG;
13203 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
13209 TargetLowering::DAGCombinerInfo &DCI,
13300 LHS = DCI.DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13304 DCI.DAG.getNode(Opcode, dl, MVT::i32, LHS, RHS->getOperand(0));
13308 Reduction = DCI.DAG.getNode(ISD::TRUNCATE, dl, VectorScalarType, Reduction);
13428 TargetLowering::DAGCombinerInfo &DCI,
13433 if (SDValue V = PerformVQDMULHCombine(N, DCI.DAG))
13463 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS);
13468 TargetLowering::DAGCombinerInfo &DCI,
13476 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
13497 SDValue Op1S = DCI.DAG.getSplatValue(Op1);
13520 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13521 DCI.DAG.getConstant(Opc, DL, MVT::i32),
13522 DCI.DAG.getZExtOrTrunc(Op1S, DL, MVT::i32));
13529 TargetLowering::DAGCombinerInfo &DCI,
13533 return PerformAddeSubeCombine(N, DCI, Subtarget);
13536 if (DCI.isBeforeLegalize()) return SDValue();
13538 return AddCombineTo64bitUMAAL(N, DCI, Subtarget);
13546 TargetLowering::DAGCombinerInfo &DCI,
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget))
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget))
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI,
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI))
13915 TargetLowering::DAGCombinerInfo &DCI,
13918 if (DCI.isBeforeLegalize())
14005 SelectionDAG &DAG = DCI.DAG;
14023 TargetLowering::DAGCombinerInfo &DCI,
14029 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14032 if (SDValue Result = PerformADDVecReduce(N, DCI.DAG, Subtarget))
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget))
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
14066 TargetLowering::DAGCombinerInfo &DCI,
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
14076 if (SDValue R = PerformSubCSINCCombine(N, DCI.DAG))
14097 SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32,
14098 DCI.DAG.getConstant(0, dl, MVT::i32),
14100 return DCI.DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), Negate);
14119 TargetLowering::DAGCombinerInfo &DCI,
14124 SelectionDAG &DAG = DCI.DAG;
14215 TargetLowering::DAGCombinerInfo &DCI,
14217 SelectionDAG &DAG = DCI.DAG;
14226 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14230 return PerformVMULCombine(N, DCI, Subtarget);
14296 DCI.CombineTo(N, Res, false);
14301 TargetLowering::DAGCombinerInfo &DCI,
14304 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14342 SelectionDAG &DAG = DCI.DAG;
14413 TargetLowering::DAGCombinerInfo &DCI,
14419 SelectionDAG &DAG = DCI.DAG;
14447 if (SDValue Result = combineSelectAndUseCommutative(N, true, DCI))
14450 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14455 if (SDValue Result = CombineANDShift(N, DCI, Subtarget))
14463 TargetLowering::DAGCombinerInfo &DCI,
14500 SelectionDAG &DAG = DCI.DAG;
14523 TargetLowering::DAGCombinerInfo &DCI,
14532 SelectionDAG &DAG = DCI.DAG;
14574 DCI.CombineTo(N, Res, false);
14601 DCI.CombineTo(N, Res, false);
14618 DCI.CombineTo(N, Res, false);
14639 DCI.CombineTo(N, Res, false);
14706 TargetLowering::DAGCombinerInfo &DCI,
14712 SelectionDAG &DAG = DCI.DAG;
14743 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
14745 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget))
14795 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget))
14799 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
14806 TargetLowering::DAGCombinerInfo &DCI,
14809 SelectionDAG &DAG = DCI.DAG;
14816 if (SDValue Result = combineSelectAndUseCommutative(N, false, DCI))
14819 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget))
15054 TargetLowering::DAGCombinerInfo &DCI,
15059 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
15070 SelectionDAG &DAG = DCI.DAG;
15086 if (DCI.DAG.getDataLayout().isBigEndian())
15088 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
15119 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N));
15137 return DCI.DAG.getMergeValues({Op0, Op1}, SDLoc(N));
15162 TargetLowering::DAGCombinerInfo &DCI) {
15186 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N),
15187 DCI.DAG.getVTList(ArrayRef(OutTys, HasGlue ? 3 : 2)),
15191 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), NewCopy.getValue(0));
15192 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(1), NewCopy.getValue(1));
15194 DCI.DAG.ReplaceAllUsesOfValueWith(Copy.getValue(2),
15206 DCI.DAG.getLoad(N->getValueType(0), SDLoc(N), LN0->getChain(),
15208 DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0));
15209 DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1));
15216 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
15217 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI))
15271 TargetLowering::DAGCombinerInfo &DCI,
15277 SelectionDAG &DAG = DCI.DAG;
15294 DCI.AddToWorklist(V.getNode());
15303 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15356 SelectionDAG &DAG = DCI.DAG;
15382 DCI.AddToWorklist(V.getNode());
15389 DCI.AddToWorklist(Vec.getNode());
15394 PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15404 return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
15411 DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
15412 SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,
15413 DCI.DAG.getConstant(65535, dl, MVT::i32));
15414 return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C);
15420 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
15421 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
15485 TargetLowering::DAGCombinerInfo &DCI) {
15494 SelectionDAG &DAG = DCI.DAG;
15501 DCI.AddToWorklist(Vec.getNode());
15502 DCI.AddToWorklist(V.getNode());
15513 PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15517 if (!DCI.isAfterLegalizeDAG() || VT != MVT::i32 ||
15518 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(MVT::f64))
15563 SDValue F64 = DCI.DAG.getNode(
15565 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0),
15566 DCI.DAG.getConstant(Ext.getConstantOperandVal(1) / 2, dl, MVT::i32));
15568 DCI.DAG.getNode(ARMISD::VMOVRRD, dl, {MVT::i32, MVT::i32}, F64);
15570 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1));
15575 TargetLowering::DAGCombinerInfo &DCI,
15585 return DCI.DAG.getNode(ARMISD::VMOVhr, dl, VT, X);
15587 return DCI.DAG.getNode(ARMISD::VMOVrh, dl, VT, X);
15589 return DCI.DAG.getNode(ISD::BITCAST, dl, VT, X);
15618 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI))
15628 return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Op0.getOperand(Vec),
15629 DCI.DAG.getConstant(SubIdx, dl, MVT::i32));
15650 PerformInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
15659 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(VecVT) ||
15660 !DCI.DAG.getTargetLoweringInfo().isTypeLegal(SubVT))
15680 Hi = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec,
15681 DCI.DAG.getVectorIdxConstant(NumSubElts, DL));
15683 Lo = DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, Vec,
15684 DCI.DAG.getVectorIdxConstant(0, DL));
15687 return DCI.DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi);
15790 TargetLowering::DAGCombinerInfo &DCI) {
15791 SelectionDAG &DAG = DCI.DAG;
16082 DCI.CombineTo(N, NewResults);
16083 DCI.CombineTo(User.N, SDValue(UpdN.getNode(), NumResultVecs));
16157 TargetLowering::DAGCombinerInfo &DCI) {
16178 getPointerConstIncrement(User->getOpcode(), Addr, Inc, DCI.DAG);
16190 getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG);
16201 getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG);
16207 SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32);
16225 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/true, DCI))
16239 if (TryCombineBaseUpdate(Target, User, /*SimpleConstIncOnly=*/false, DCI))
16246 TargetLowering::DAGCombinerInfo &DCI) {
16247 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16250 return CombineBaseUpdate(N, DCI);
16254 TargetLowering::DAGCombinerInfo &DCI) {
16255 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16258 SelectionDAG &DAG = DCI.DAG;
16364 DCI.CombineTo(N, NewResults);
16365 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
16377 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
16378 SelectionDAG &DAG = DCI.DAG;
16439 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
16448 DCI.CombineTo(VLD, VLDDupResults);
16456 TargetLowering::DAGCombinerInfo &DCI,
16465 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT))
16467 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT,
16469 return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract);
16474 if (CombineVLDDUP(N, DCI))
16494 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
16537 TargetLowering::DAGCombinerInfo &DCI,
16543 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
16544 return CombineBaseUpdate(N, DCI);
16807 TargetLowering::DAGCombinerInfo &DCI,
16816 if (SDValue Store = PerformTruncatingStoreCombine(St, DCI.DAG))
16820 if (SDValue NewToken = PerformSplittingToNarrowingStores(St, DCI.DAG))
16824 if (SDValue NewChain = PerformExtractFpToIntStores(St, DCI.DAG))
16827 PerformSplittingMVETruncToNarrowingStores(St, DCI.DAG))
16838 SelectionDAG &DAG = DCI.DAG;
16861 SelectionDAG &DAG = DCI.DAG;
16872 DCI.AddToWorklist(Vec.getNode());
16873 DCI.AddToWorklist(ExtElt.getNode());
16874 DCI.AddToWorklist(V.getNode());
16882 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
16883 return CombineBaseUpdate(N, DCI);
17389 TargetLowering::DAGCombinerInfo &DCI) {
17407 return DCI.DAG.getNode(Op1->getOpcode(), SDLoc(Op1), N->getValueType(0),
17419 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17420 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
17422 if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI))
17429 TargetLowering::DAGCombinerInfo &DCI) {
17438 const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
17439 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
17445 TargetLowering::DAGCombinerInfo &DCI) {
17457 SDValue NewBinOp = DCI.DAG.getNode(N->getOpcode(), DL, VT,
17460 return DCI.DAG.getVectorShuffle(VT, DL, NewBinOp, UndefV, Shuf0->getMask());
17495 DAGCombinerInfo &DCI) const {
17496 SelectionDAG &DAG = DCI.DAG;
17662 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI))
17679 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
17722 TargetLowering::DAGCombinerInfo &DCI,
17724 SelectionDAG &DAG = DCI.DAG;
17730 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
18221 TargetLowering::DAGCombinerInfo &DCI,
18286 SelectionDAG &DAG = DCI.DAG;
18570 TargetLowering::DAGCombinerInfo &DCI,
18572 SelectionDAG &DAG = DCI.DAG;
18599 if (SDValue R = PerformExtractEltToVMOVRRD(N, DCI))
18608 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
18609 SelectionDAG &DAG = DCI.DAG;
18678 if (!DCI.isAfterLegalizeDAG())
18777 SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
18778 SelectionDAG &DAG = DCI.DAG;
18844 if (!DCI.isAfterLegalizeDAG())
18881 DAGCombinerInfo &DCI) const {
18885 case ISD::SELECT: return PerformSELECTCombine(N, DCI, Subtarget);
18886 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget);
18887 case ISD::SETCC: return PerformVSetCCToVCTPCombine(N, DCI, Subtarget);
18888 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget);
18889 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget);
18890 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
18891 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget);
18892 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
18893 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
18894 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
18895 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
18897 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
18899 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget);
18900 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget);
18901 case ARMISD::BFI: return PerformBFICombine(N, DCI.DAG);
18902 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
18903 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
18904 case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI);
18905 case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI.DAG);
18906 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget);
18907 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
18908 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
18910 return PerformExtractEltCombine(N, DCI, Subtarget);
18911 case ISD::SIGN_EXTEND_INREG: return PerformSignExtendInregCombine(N, DCI.DAG);
18912 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI);
18913 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
18914 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget);
18915 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI.DAG, Subtarget);
18918 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
18920 return PerformFADDCombine(N, DCI.DAG, Subtarget);
18922 return PerformVMulVCTPCombine(N, DCI.DAG, Subtarget);
18924 return PerformIntrinsicCombine(N, DCI);
18928 return PerformShiftCombine(N, DCI, Subtarget);
18932 return PerformExtendCombine(N, DCI.DAG, Subtarget);
18934 return PerformFPExtendCombine(N, DCI.DAG, Subtarget);
18939 return PerformMinMaxCombine(N, DCI.DAG, Subtarget);
18941 return PerformCMOVCombine(N, DCI.DAG);
18943 return PerformBRCONDCombine(N, DCI.DAG);
18945 return PerformCMPZCombine(N, DCI.DAG);
18949 return PerformCSETCombine(N, DCI.DAG);
18951 return PerformLOADCombine(N, DCI, Subtarget);
18956 return PerformVLDCombine(N, DCI);
18958 return PerformARMBUILD_VECTORCombine(N, DCI);
18960 return PerformBITCASTCombine(N, DCI, Subtarget);
18962 return PerformPREDICATE_CASTCombine(N, DCI);
18964 return PerformVECTOR_REG_CASTCombine(N, DCI.DAG, Subtarget);
18966 return PerformMVETruncCombine(N, DCI);
18969 return PerformMVEExtCombine(N, DCI);
18971 return PerformVCMPCombine(N, DCI.DAG, Subtarget);
18973 return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget);
18986 return PerformReduceShuffleCombine(N, DCI.DAG);
18988 return PerformVMOVNCombine(N, DCI);
18991 return PerformVQMOVNCombine(N, DCI);
18993 return PerformVQDMULHCombine(N, DCI);
18997 return PerformLongShiftCombine(N, DCI.DAG);
19001 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
19008 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))
19019 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19020 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19029 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) ||
19030 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI)))
19039 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) ||
19040 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI)))
19047 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19048 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19058 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
19059 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
19089 return PerformVLDCombine(N, DCI);
19094 return PerformMVEVLDCombine(N, DCI);