Lines Matching defs:Reg0

2173   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2192       // VLD1/VLD2 fixed increment does not need Reg0 so only include it in
2195         Ops.push_back(Reg0);
2198     Ops.push_back(Reg0);
2211     const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
2224       Ops.push_back(Reg0);
2228     Ops.push_back(Reg0);
2308   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2352       // VST1/VST2 fixed increment does not need Reg0 so only include it in
2355         Ops.push_back(Reg0);
2359     Ops.push_back(Reg0);
2384   const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2399     Ops.push_back(Reg0);
2403   Ops.push_back(Reg0);
2480   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2489     Ops.push_back(IsImmUpdate ? Reg0 : Inc);
2513   Ops.push_back(Reg0);
3018   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3032         Ops.push_back(Reg0);
3044     const SDValue OpsA[] = {MemAddr, Align, ImplDef, Pred, Reg0, Chain};
3052   Ops.push_back(Reg0);
3367         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3375                               getAL(CurDAG, dl), Reg0, Reg0 };
3386                             getAL(CurDAG, dl), Reg0, Reg0 };
3395                           getAL(CurDAG, dl), Reg0 };
3415       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3420                         getAL(CurDAG, dl), Reg0 };
3437       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3442                         getAL(CurDAG, dl), Reg0 };
3458     SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3463                       getAL(CurDAG, dl), Reg0 };
3808         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3810           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3814           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3815                             Reg0 };
3827         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
3829           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3833           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3834                             Reg0 };
5192       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
5193       SDValue Ops[] = { Src, Src, Pred, Reg0 };
5203       SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
5204       SDValue Ops[] = { Src, Pred, Reg0 };
5782     Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
5804       SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
5818       SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,